Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 355
Power Management
Entry and exit of the C-States at the thread and core level are shown in Figure 69.
While individual threads can request low power C-states, power-saving actions only
take place after the core C-state is resolved. The processor automatically resolves Core
C-states. For thread and core C-states, a transition to and from C0 is required before
entering any other C-state.
Note:
1. If enabled, the core C-state will be C1E if all active cores have also resolved to a core C1 state or higher.
8.2.3 Requesting Low-Power Idle States
The primary software interfaces for requesting low power idle states are through the
MWAIT instruction with sub-state hints and the HLT instruction (for C1E). However,
software may make C-state requests using the legacy method of I/O reads from the
ACPI-defined processor clock control registers, referred to as P_LVLx. This method of
requesting C-states provides legacy support for operating systems that initiate C-state
transitions via I/O reads.
For legacy operating systems, P_LVLx I/O reads are converted within the processor to
the equivalent MWAIT C-state request. Therefore, P_LVLx reads do not directly result in
I/O reads to the system. The feature, known as I/O MWAIT redirection, must be
enabled in the BIOS.
Figure 69. Thread and Core C-State Entry and Exit
C1E C6C3
C0C0
MWAIT(C6),
P_LVL3 I/O Read
MWAIT(C3),
P_LVL2 I/O Read
MWAIT(C1), HLT
(C1E Enabled)
Table 121. Coordination of Thread Power States at the Core Level
Processor Core
C-State
Thread 1
C0 C1E C3 C6
Thread 0
C0 C0 C0 C0 C0
C1E C0 C1E
1
C1E
1
C1E
1
C3 C0 C1E
1
C3 C3
C6 C0 C1E
1
C3 C6