Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 353
Power Management
8.1.10 Supported DMI Power States
The transitions to and from the following power management states are supported on
the DMI link:
8.2 Processor Core Power Management
While executing code, Enhanced Intel Speedstep
®
Technology optimizes the
processor’s frequency and core voltage based on workload. Each frequency and voltage
operating point is defined by ACPI as a P-state. The processor is idle when not
executing code. ACPI defines a low-power idle state as a C-state. In general, lower
power C-states have longer entry and exit latencies.
8.2.1 Enhanced Intel SpeedStep
®
Technology
The following are key features of Enhanced Intel SpeedStep
®
Technology:
• Multiple frequency and voltage points for optimal performance and power
efficiency. These operating points are known as P-states.
• Frequency selection is software-controlled by writing to processor MSRs. The
voltage is optimized based on the selected frequency and the number of active
processor cores.
— If the target frequency is higher than the current frequency and a voltage
change is required, the voltage is ramped up in steps to an optimized voltage.
This voltage is signaled by the VID[7:0] pins to the voltage regulator. Once the
voltage is established, the PLL locks on to the target frequency.
— If the target frequency is lower than the current frequency, then the PLL locks
to the target frequency, then, if needed, transitions to a lower voltage by
signaling the target voltage on the VID[7:0] pins.
— All active processor cores share the same frequency and voltage. In a multi-
core processor, the highest frequency P-state requested amongst all active
cores is selected.
— Software-requested transitions are accepted at any time. If a previous
transition is in progress, then the new transition is deferred until the previous
transition is completed.
• The processor controls voltage ramp rates internally to ensure glitch-free
transitions.
Table 120. System and DMI Link Power States
System
State
CPU
State
Description Link State Comments
S0 C0
Fully operational /
Opportunistic Link Active-State
L0/L0s/L1a
1
1. L1a means active state L1 in the DMI specification
Active-State Power
Management
S0 C1E
2
2. The “E” suffix denotes additional minimum voltage-frequency P-state.
CPU Auto-Halt L0/L0s/L1a
Active-State Power
Management
S0 C3/C6 Deep Sleep States L0/L0s/L1a
Active-State Power
Management
S1 C1E/C3
The legacy association of S1
with C2 is no longer valid.
L0/L0s/L1a
Active-State Power
Management
S3/S4/S5 N/A STR/STD/Off L3
Requires Reset. System
context not maintained in S5.