Datasheet

Power Management
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
352 Order Number: 323103-001
8.1.6 DMI States
8.1.7 Intel
®
QPI States
8.1.8 Intel
®
QuickData Technology State
8.1.9 Interface State Combinations
Table 116. DMI States
State Description
L0 Full on – Active transfer state.
L0s First Active Power Management low power state – Low exit latency.
L1a L1a is active state L1 in the DMI Specification.
L3 Lowest power state (power-off) – Longest exit latency.
Table 117. Intel
®
QPI States
State Description
L0s First Active Power Management low power state – Low exit latency.
L1 Lowest Active Power Management - Longer exit latency.
Table 118. Intel
®
QuickData Technology States
State Description
D0 Fully-on state and a pseudo D3hot state.
Table 119. G, S, and C State Combinations
Global
(G) State
Sleep
(S) State
Processor
Core
(C) State
Processor
State
System Clocks Description
G0 S0 C0 Full On On Full On
G0 S0 C1E Auto-Halt On Auto-Halt
G0 S0 C3 Deep Sleep On Deep Sleep
G0 S0 C6
Deep Power
Down
On Deep Power Down
G1 S3 Power off Off, except RTC Suspend to RAM
G1 S4 Power off Off, except RTC Suspend to Disk
G2 S5 Power off Off, except RTC Soft Off
G3 NA Power off Power off Hard off