Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 351
Power Management
The IIO module supports the S0 (fully active) state. This is required for full operation.
The IIO module also supports a system level S1 (idle) state, but the S2 (power-on
suspend) is not supported. The IIO module supports S3/S4/S5 powered-down idle
sleep states. In the S3 state (suspend to RAM), the context is preserved in memory by
the OS and the CPU places the memory in self-refresh mode to prevent data loss. In
the S4/S5 states, platform power and clocking are disabled, leaving only one or more
auxiliary power domains functional. Exit from the S3, S4, and S5 states requires a full
system reset and initialization sequence.
8.1.3 Processor Core/Package States
Core: C0, C1E, C3, C6
Package C0, C3, C6
Enhanced Intel SpeedStep
®
Technology
8.1.4 Integrated Memory Controller States
8.1.5 PCIe Link States
S3
Suspend to RAM (STR) [Supported]
This is also known as Standby. CPU, and PCI reset. All context can be lost except memory.
This state is commonly known as “Suspend”.
S4
Suspend to Disk (STD) [Supported]
CPU, PCI and Memory reset. The S4 state is similar to S3 except that the system context is
saved to disk rather that main memory. This state is commonly known as “Hibernate”. Self
Refresh is not required.
S5
Soft off [Supported]
Power removed.
Table 113. Platform System States (Sheet 2 of 2)
System State Description
Table 114. Integrated Memory Controller States
State Description
Power up CKE asserted. Active mode.
Pre-charge Power down CKE deasserted (not self-refresh) with all banks closed.
Active Power down CKE deasserted (not self-refresh) with minimum one bank active.
Self-Refresh CKE deasserted using device self-refresh.
Table 115. PCIe Link States
State Description
L0 Full on – Active transfer state.
L0s First Active Power Management low power state – Low exit latency.
L1 Lowest Active Power Management - Longer exit latency.
L3 Lowest power state (power-off) – Longest exit latency.