Datasheet

Power Management
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
350 Order Number: 323103-001
8.1.2 Supported System Power States
The system power states supported by the Intel
®
Xeon
®
processor C5500/C3500
series IIO module are enumerated in Table 113.
Figure 67. ACPI Power States in G0, G1, and G2 States
C0C-States
S0
S5
Soft Off
Processor States
Pn
P1
P0
S4
S3
S1
Idle Time
Wake Event
Stop Grant
Suspend to RAM
Suspend to Disk
System States
Performance States
Voltage/Frequency
Combination
G0 State: System State S0. Core State can be C0...Cx.
In C0 state, P states can be P0...Pn
G1 State: System State can be S1, S3 or S4
G2 State: System state will be S5
G3 State: Power Off
Higher
Power
Lower
Power
Table 113. Platform System States (Sheet 1 of 2)
System State Description
S0
Full On: [Supported by the IIO module]
Normal operation
S1
Stop-Grant: [Supported by the IIO module]
No reset or re-enumeration required.
Context preserved in caches and memory.
Processor cores go to a low power idle state. See Table 120 for details.
After leaving only one “monarch” thread alive among all threads in all sockets, system
software initiates an I/O write to the SLP_EN bit in the PCH’s power management control
register (PMBase + 04h) and then halts the “monarch”. This will cause the PCH to send the
GO_S1_final DMI2 message to the IIO module. The IIO module responds with a NcMsgB-
PMREQ(‘S1) handshake with the CPU’s followed by an ACK_Sx DMI2 message to the PCH.
(The “monarch” is the thread that executes the S-state entry sequence.) See text for the
IIO module sequence.