Datasheet
Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 35
Interfaces
2.0 Interfaces
This chapter describes the interfaces supported by the processor.
2.1 System Memory Interface
The complete list of supported memory configurations is preliminary, and is subject to
change before product launch.
2.1.1 System Memory Technology Supported
The Intel
®
Xeon
®
processor C5500/C3500 series contains an integrated memory
controller (IMC). The memory interface supports up to three DDR3 channels. Each
channel consists of 64 bit data and 8 ECC bits. Up to three DIMMs can be connected to
each DDR3 channel for a total of nine DIMMs per socket. The IMC supports DDR3 800
MT/s, DDR3 1066 MT/s and DDR3 1333 MT/s memory technologies. Three DIMMs can
only be supported at 800 MT/s.
The processor supports up to three DIMMs per channel for single-rank and/or dual-rank
DIMMs, and two DIMMs per channel for quad-rank DIMMs. See Table 6 through Table 8
for the supported configurations. A single system can be designed to support both
single-rank and dual-rank configurations. To support both, three dual-rank DIMM
configurations and two quad-rank DIMM configurations, and several control signals
must be shared amongst DIMM connectors. The guidelines for control signal topologies
are provided in the Picket Post Platform Design Guide.
Both registered ECC DDR3 DIMMs and Unbuffered DDR3 DIMMs are supported.
(Unbuffered and registered DIMMs cannot be mixed.) Table 6 lists key IMC features,
and Table 7 through Table 8 summarize the Intel
®
Xeon
®
processor C5500/C3500
series key differences for Unbuffered/Registered DIMM support.
Table 6. System Memory Feature Summary (Sheet 1 of 2)
Feature Unbuffered DDR3
Independent Registered
DDR3
Lockstepped Registered
DDR3
Physical Channels per CPU Socket 3
# Channels in use per CPU socket 1, 2, 3 2
DIMM Technology DDR3 Unbuffered DDR3 Registered
ECC Support ECC and non-ECC DIMMs
Banks per Rank Eight Independent
DRAM Speeds 800, 1067, 1333
DRAM Sizes 1 Gb, 2 Gb, 4 Gb
DIMMs per Channel 1, 2 1, 2, 3
Command/Address Rate 1N(1xCK), 2N(1/2xCK);
Max Ranks per Channel 8
Ranks per DIMM 1, 2 1, 2, 4