Datasheet

Interrupts
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
348 Order Number: 323103-001
7.6.1 Legacy Interrupt Handled By IIO Module IOxAPIC
When an INTx interrupt is enabled within the IIO module IOxAPIC, then the IIO module
IOxAPIC may be programmed to deliver the legacy interrupt depending on the mask :
There is no mode in which the integrated IOxAPIC delivers a legacy interrupt directly to
the CPU.
If the legacy interrupt is converted to an MSI interrupt, and the Intel
®
VT-d engine is
enabled, then the Intel
®
VT-d engine can be programmed to perform an interrupt
address translation before delivering the interrupt to a core.
7.6.2 MSI Interrupt
MSI interrupts do not need the support of an IOxAPIC, they are routed as a message
directly to the intended core. If the Intel
®
VT-d engine is enabled, it can be
programmed to perform an interrupt address translation before delivering the interrupt
to a core.
§ §
Mask DRTPCH Behavior
0 X Convert to MSI
10Forward INTx to PCH
1 1 Pend INTx in IOxAPIC