Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 347
Interrupts
APICs that were not specifically addressed will drop the message. There are two per
core and one per thread, yielding eight local APICs in Intel
®
Xeon
®
processor C5500/
C3500 series when all four cores with SMT are enabled.
7.5 Platform Interrupts
General Purpose Event (GPE) interrupts are generated as a result of hot plug and power
management events. GPE interrupts are conveyed as VLW messages routed to the
IOxAPIC within the PCH. In response to a GPE VLW, the PCH IOxAPIC can be
programmed to send out an MSI message or legacy INTx interrupt. Either socket could
be the destination of the interrupt message. The IIO module tracks and maintains the
state of the three level-sensitive GPE messages (Assert/Deassert_GPE, Assert/
Deassert_HPGPE, Assert/Deassert_PMEGPE). The legacy IIO module (the processor
socket that directly connects to the PCH component) has this responsibility.
Various RAS events and errors can cause an IntPhysical PMI/SMI/NMI interrupt to be
generated directly to the processor, bypassing the PCH.
All Correctable Platform Event Interrupts (CPEI) are routed to the IIO module. This
includes PCIe-corrected errors if native handling of these errors has been disabled by
the OS. In the case of a Intel
®
Xeon
®
processor C5500/C3500 series DP system,
corrected errors detected by the non-legacy IIO module are routed to the legacy IIO
module. The IIO module combines the corrected error messages from all sources and
generates a CPEI message based on the SYSMAP register.
The legacy Intel
®
Xeon
®
processor C5500/C3500 series socket maintains a pin
(ERR[0]) that represents the state of CPEI. Software can read a status bit (bit 0 of
register ERRPINST: Error Pin Status Register) to detect the state of the ERR[0] pin.
Once the pin has been set, further CPEI events have no effect. The status bit needs to
be reset to detect any additional CPEI events. The ERR[0] pin of the legacy Intel
®
Xeon
®
processor C5500/C3500 series can be connected to the PCH to signal the
IOxAPIC within the PCH to generate an INTx or MSI interrupt.
7.6 Interrupt Flow
The PCH contains an integrated IOxAPIC and additional downstream external IOxAPICs
are supported.
Additionally, each Intel
®
Xeon
®
processor C5500/C3500 series contains its own
IOxAPIC, in addition to the IOxAPIC that is resident in the PCH, or any additional
downstream external IOxAPICs. As a result, the processor supports a flexible interrupt
architecture. Interrupts from one socket can be handled by the integrated IOxAPIC
within the socket, or may be programmed to be handled by the IOxAPIC within the
PCH.
At power-up the Redirection Table Entries (RTE) are masked, the integrated IOxAPIC is
unprogrammed, and the Don’t_Route_To_PCH bit is reset so all legacy INTx interrupts
are routed to the PCH’s IOxAPIC.
When an INTx interrupt is disabled within the IIO module IOxAPIC, then legacy INTx
interrupts are routed to the PCH IOxAPIC, regardless of the originating socket (legacy
or non-legacy). The PCH IOxAPIC can then be programmed to deliver the legacy
interrupt to any core within either socket, or to convert the legacy interrupt into an MSI
interrupt before delivery to any core within either socket. This also applies to legacy
interrupts directly received by the PCH IOxAPIC.