Datasheet

Interrupts
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
346 Order Number: 323103-001
The IIO adds a value of 2 to the original selected APICs address bit location. If the
APIC corresponding to modulo 8 of that value is also not a valid target, then the IIO
adds a value of 4 to the previous value and takes the modulo 8 of the resulting
value. If that corresponding APIC is also not a valid target, then,
The IIO adds a value of 3 to the original selected APICs address bit location. If the
APIC corresponding to modulo 8 of that value is also not a valid target, then the IIO
adds a value of 4 to the previous value and takes the modulo 8 of the resulting
value. If that corresponding APIC is also not a valid target, then,
The IIO adds a value of 1 to original selected APICs address bit location. If the APIC
corresponding to modulo eight of that value is also not a valid target, then IIO adds
a value of 4 to the previous value and takes the modulo 8 of the resulting value. If
that corresponding APIC is also not a valid target, then it is an error condition.
In logical cluster mode (except when APICID[19:16] != F), the redirection algorithm
works as described above except the IIO only redirects between four APICs instead of
eight in the flat mode. Therefore, the IIO uses only vector number bits [5:4] by default
(selectable to bits[4:3]/2:1/1:0 based on bits 4:3 of QPIPINTRC register). The search
algorithm to identify a valid APIC for redirection in the cluster mode is to:
First select the APIC that corresponds to the bit position identified with the chosen
vector number bits. If corresponding bit in the MSI address bits A[15:12] is clear,
then,
The IIO adds a value of 2 to the original selected APICs address bit location. If the
APIC corresponding to modulo four of that value is also not a valid target, then
The IIO adds a value of 1 to original selected APICs address bit location. If the APIC
corresponding to modulo 4 of that value is also not a valid target, then the IIO adds
a value of 2 to the previous value and takes the modulo 4 of the resulting value. If
that corresponding APIC is also not a valid target, then it is an error condition.
7.3.3 External IOxAPIC Support
External IOxAPICs, such as those within a PXH, PCH, etc. are supported. These devices
require special decoding of a fixed address range FECx_xxxx in the IIO module. The IIO
module provides these decoding ranges, which are outside the normal prefetchable and
non-prefetchable windows supported in each root port. More information is in the
chapter on System Address Maps.
The local APIC supports EOI messages to external IOxAPICs that need the EOI
message. It also supports EOI messages to the internal IOxAPIC. The IIO module, if
enabled, can be programmed to broadcast/multicast the EOI message to all
downstream PCIe/DMI ports. The broadcast/multicast of the EOI message is also
supported for the internal IOxAPIC. The EOI message can be disabled globally using
the global EOI disable bit in the EOI_CTRL register of Device #0, or can be disabled on
a per PCIe/DMI port basis.
7.4 Virtual Legacy Wires (VLW)
Discrete signals that existed on previous-generation processors (e.g.: NMI/SMI#/INTR/
INIT#/A20M#/FERR#, etc.) are now implemented as messages. This capability is
referred to as “Virtual Legacy Wires” or “VLW Messages”. Signals that were discrete
wires that went between the PCH and the processor are now communicated using
Vendor Defined messages over the DMI interface.
In DP configurations the Vendor Defined messages are broadcast to both processor
sockets. The message is routed over the Intel
®
QPI bus to the non-legacy socket. Only
the destined local APIC of one processor socket claims the VLW message; all other local