Manualshelf

Datasheet

ManualsBrandsIntel Manualscomputer componentsAT80612002931AB
341342343344345346347348349350
Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 345
Interrupts
The Destination ID shown in the above illustration becomes the APICID on the Intel
®
QuickPath Interconnect interrupt packet.
7.3.2 MSI Forwarding: IA32 Processor-based Platform
IA-32 interrupts have two modes: legacy mode and extended mode. Legacy mode has
been supported in all chipsets to date. Extended mode is a new mode that allows for
scaling beyond 60/255 threads in logical/physical mode operation. Legacy mode has
only an 8-bit APICID; extended mode supports 32-bit APICID (obtained via IRTE).
7.3.2.1 Legacy Logical Mode Interrupts
The IIO broadcases IA32 legacy logical interrupts to all processors in the system. It is
the responsibility of the CPU to drop interrupts that are not directed to one of its local
APICs. The IIO supports hardware redirection for IA32 logical interrupts (see
Section 7.3.2.1.1) For IA32 logical interrupts, no fixed mapping is guaranteed between
the NodeID and the APICID since APICID is allocated by the OS and it has no notion of
the Intel
®
QuickPath Interconnect NodeID. The assumption is made that the APICID
field in the MSI address only includes valid/enabled APICs for that interrupt.
7.3.2.1.1 Legacy Logical Mode Interrupt Redirection - Redirection Based on Vector
Number
In logical flat mode when redirection is enabled, the IIO looks at bits [6:4] (or 5:3/3:1/
2:0 based on bits 4:3 of QPIPINTRC register) of the interrupt vector number and picks
the APIC in the bit position (in the APICID field of the MSI address) that corresponds to
the vector number. For example, if vector number[6:4] is 010, then the APIC
corresponding to MSI Address APICID[2] is selected as the target of redirection. If
vector number[6:4] is 111, then the APIC correspond to APICID[7] is selected as the
target of redirection. If the corresponding bit in the MSI address is clear in the received
MSI interrupt, then:
• The IIO adds a value of 4 to the selected APICs address bit location. If the APIC
corresponding to modulo 8 of that value is also not a valid target because the bit
mask corresponding to that APIC is clear in the MSI address, then,
Figure 66. Interrupt Transformation Table Entry (IRTE)