Datasheet

Interrupts
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
344 Order Number: 323103-001
All PCI Express devices are required to support MSI. The IIO converts memory writes to
this address (both PCI Express and internal sources) as a IntLogical, IntPhysical
transactions on the Intel
®
QuickPath Interconnect.
The IIO module supports two MSI vectors per root port for hot plug, power
management, and error reporting.
7.3.1 Interrupt Remapping
Interrupt remapping architecture provides for interrupt filtering for virtualization/
security usages so an arbitrary device cannot interrupt an arbitrary processor in the
system.
When interrupt remapping is enabled in the IIO, then the IIO looks up a table in main
memory to obtain the interrupt target processor and vector number. When the IIO
receives an MSI interrupt in which the MSI interrupt is any memory write interrupt
directly generated by an IO device or generated by an I/OxAPIC like the integrated
I/OxAPIC in IIO/PCH, and the remapping is turned on, then the IIO picks up the
‘interrupt handle’ field from the MSI (bits 19:4 of the MSI address) and adds it to the
sub handle field in the MSI data field, if the sub handle valid field in the MSI address is
set, to obtain the final interrupt handle value. The final interrupt handle value is then
used as an offset into the table in main memory as:
Memory Offset = Final Interrupt Handle * 16
where Final Interrupt Handle = if (Sub Handle Valid = 1) then {Interrupt Handle + Sub
Handle} else Interrupt Handle.
The data obtained from the memory lookup is called the Interrupt Transformation Table
Entry (IRTE).
The information that was formerly obtained directly from the MSI address/data fields is
now obtained via the IRTE when remapping is turned on. In addition, the IRTE also
provides a way to authenticate an interrupt via the Requester ID, i.e. the IIO needs to
compare the Requester ID in the original MSI interrupt packet that triggered the lookup
with the Requester ID indicated in the IRTE. If it matches, then the interrupt is further
processed, else the interrupt is dropped and error signaled. Subsequent sections in this
chapter describe how fields in either the IRTE when remapping is enabled, or MSI
address/data when remapping is disabled, are used by the chipset to generate
IntPhysical/Logical interrupts on Intel
®
QuickPath Interconnect.
Table 112. MSI Data Format when Remapping is Enabled
Bits Description
31:16
Reserved - IIO hardware checks for this field to be 0 (note that this
checking is done only when remapping is enabled
15:0 Sub Handle