Datasheet

Interrupts
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
342 Order Number: 323103-001
determines further action. This guarantees that any MSI generated from the integrated
I/OxAPIC, or from the I/OxAPIC in PCH, if the integrated I/OxAPIC is disabled, will be
ordered behind the memory write A, guaranteeing producer/consumer sanity.
7.2.3 INTR_Ack/INTR_Ack_Reply Messages
INTR_Ack and INTR_Ack_Reply messages on DMI and IntAck on Intel
®
QuickPath
Interconnect support legacy 8259-style interrupts required for system boot operations.
These messages are routed from the processor socket to the legacy IIO via the IntAck
cycle on Intel
®
QuickPath Interconnect. The IntAck transaction issued by the processor
socket behaves as an IO read cycle in that the completion for the IntAck message
contains the interrupt vector. The IIO converts this cycle to a posted message on the
DMI port (no completions).
• IntAck: The IIO forwards the IntAck received on the Coherent Interface (as an NCS
transaction) as a posted message INTR_Ack to legacy PCH over DMI. A completion
for IntAck is not yet sent on Intel
®
QuickPath Interconnect.
• INTR_Ack_Reply: The PCH returns the 8-bit interrupt vector from the 8259
controller through this posted VDM. The INTR_Ack_Reply message pushes
upstream writes in both the PCH and the IIO. This IIO then uses the data in the
INTR_Ack_Reply message to form the completion for the original IntAck message.
Note: There can be only one outstanding IntAck transaction across all processor sockets in a
partition at a given instance.
7.3 MSI
Note: The term APICID in this chapter refers to the 32-bit field on Intel
®
QuickPath
Interconnect interrupt packets in both the format and meaning.
MSI interrupts generated from PCI Express ports or from integrated functions within
the IIO are memory writes to a specific address range, 0xFEEx_xxxx. If interrupt
remapping is disabled in the IIO, then the interrupt write directly provides the
information regarding the interrupt destination processor and interrupt vector. Details
are as shown in Table 109 and Table 110. If interrupt remapping is enabled in the IIO,
then interrupt write fields are interpreted as shown in Table 111 and Table 112.
Table 109. MSI Address Format when Remapping Disabled (Sheet 1 of 2)
Bits Description
31:20 FEEh
19:12
Destination ID: This will be the bits 63:56 of the I/O Redirection Table
entry for the interrupt associated with this message.
In IA32 mode:
For physical mode interrupts, this field becomes APICID[7:0] on the QPI
interrupt packet and APICID[31:8] are reserved in the QPI packet.
For logical cluster mode interrupts, 19:16 of this field becomes
APICID[19:16] on the QPI interrupt packet and 15:12 of this field becomes
APICID[3:0] on the QPI interrupt packet.
For logical flat mode interrupts, 19:12 of this field becomes APICID[7:0] on
the QPI interrupt packet.
11:4
EID: this will be the bits 55:48 of the I/O Redirection Table entry for the
interrupt associated with this message.