Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 341
Interrupts
7.2.1.1 Integrated I/OxAPIC EOI Flow
Software can set up each I/OxAPIC entry to treat the interrupt inputs as either level- or
edge-triggered. For level-triggered interrupts, the I/OxAPIC generates an interrupt
when the interrupt input asserts. It stops generating further interrupts until software
clears the RIRR bit in the corresponding redirection table entry with a directed write to
the EOI register or software generates an EOI message to the I/OxAPIC with the
appropriate vector number in the message. When the RIRR bit is cleared, the I/OxAPIC
resamples the level-interrupt input corresponding to the entry and if it is still asserted,
generate a new MSI message.
The EOI message is broadcast to all I/OxAPICs in the system and the integrated
I/OxAPIC in the IIO is also a target for that message. The I/OxAPIC looks at the vector
number in the message and the RIRR bit is cleared in all I/OxAPIC entries that have a
matching vector number.
The IIO has capability to NOT broadcast/multicast EOI message to any of the PCI
Express/DMI ports/integrated IOxAPIC. This is controlled via bit 0 in the EOI_CTRL
register. When this bit is set, the IIO drops the EOI message received from Intel
®
QuickPath Interconnect and does not send it to any south agent. But the IIO does send
a normal cmp for the message on Intel
®
QuickPath Interconnect. This is required in
some virtualization usages.
7.2.2 PCI Express INTx Message Ordering
INTx messages on PCI Express are posted transactions and hence must follow the
posted ordering rules. For example, if the INTx message is preceded by a memory
write A, then the INTx message must push the memory write to a global ordering point
before it is delivered to its destination, which could be the I/OxAPIC cluster that
10 2 INTD
11 3 INTA
12 3 INTB
13 3 INTD
14 4 INTA
15 4 INTB
16 4 INTC
17 5 INTB
18 5 INTC
19 5 INTD
20 6 INTA
21 6 INTC
22 1 INTC
23 1 INTB
1. < >, [ ], and { } in the table associate an interrupt from a given device number (as shown in the ‘PCI
Express Port/Intel® QuickData Technology DMA Device#’ column) that is marked thus to the corresponding
interrupt wire type (shown in this column) also marked such. For example, I/OxAPIC entry 3 corresponds
to the Wire-OR of INTD message from source#6 (Intel
®
QuickData Technology DMA INTD) and INTD
message from source#4 (PCIE port #3).
Table 108. I/OxAPIC Table Mapping to PCI Express Interrupts (Sheet 2 of 2)
I/OxAPIC Table
Entry#
Interrupt Source # in
Table 107
PCI Express Virtual Wire Type
1