Datasheet
Interrupts
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
340 Order Number: 323103-001
An IIO is not always guaranteed to have its DMI port enabled for legacy. When an IIO’s
DMI port is disabled
for legacy in non-legacy IIOs, then it has to route the INTx
messages it receives from its downstream PCI Express ports, to its coherent interface,
provided they are not serviced via the integrated I/OxAPIC.
7.2.1 Integrated I/OxAPIC
The integrated I/OxAPIC in IIO converts legacy PCI Express interrupt messages into
MSI interrupts. The I/OxAPIC appears as a PCI Express end-point device in the IIO
configuration space. The I/OxAPIC has a 24-deep table that allows for 24 unique MSI
interrupts. This table is programmed via either the MBAR memory region or the ABAR
memory region.
In legacy IIO with DMI, there are potentially 25 unique legacy interrupts possible, 4
root ports * 4 (sources #1 - #4) + 4 for Intel
®
QuickData Technology DMA (source #6)
+ 1 IIO RootPorts/core (source #8) + 4 for DMI (source #5) as shown in Table 108.
These are mapped to the 24 entries in the I/OxAPIC as shown in the table. The
distribution is based on guaranteeing that there is at least one un-shared interrupt line
(INTA) for each PCI-E port (from x16 down to x4), and two Intel
®
QuickData
Technology DMA (INTA and INTB) as a possible source of interrupt.
When a legacy interrupt asserts, an MSI interrupt is generated if the corresponding
I/OxAPIC entry is unmasked, based on the information programmed in the
corresponding I/OxAPIC table entry. Table 109, Table 110, Table 111, and Table 112
provide the format of the interrupt message generated by the I/OxAPIC based on the
table values.
Table 107. Interrupt Source in IOxAPIC Table Mapping
Interrupt Source PCI Express Port Devices INT[A-D] Used
1 PCIE Port 0 A,B,C,D/x16, x8, x4
2 PCIE Port 1 A, B, C, D /x4
3 PCIE Port 2 A, B, C, D/x8, x4
4 PCIE Port 3 A, B, C, D/x4
5 PCIE Port (DMI) A, B, C, D/x4
6
Intel
®
QuickData Technology
DMA
A, B, C, D
8Root Port A
Table 108. I/OxAPIC Table Mapping to PCI Express Interrupts (Sheet 1 of 2)
I/OxAPIC Table
Entry#
Interrupt Source # in
Table 107
PCI Express Virtual Wire Type
1
01 INTA
12 INTB
23 INTC
3 4, <6> INTD, <INTD>
45 INTA
56 INTB
61 INTD
78 INTA
82 INTA
92 INTC