Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 339
Interrupts
7.0 Interrupts
7.1 Overview
This chapter describes how interrupts are handled in the IIO module. See the Software
Developers Manual for details on how the CPUs process interrupts.
The IIO module supports both MSI and legacy PCI interrupts from its PCI Express*
ports. MSI interrupts received from PCI Express are forwarded directly to the processor
socket. Legacy interrupt messages received from PCI Express are either converted to
MSI interrupts via the integrated I/OxAPIC in the IIO or forwarded to the Direct Media
Interface (DMI) (See the section on Legacy Interrupt Handling). When legacy
interrupts are forwarded to DMI, the compatibility bridge either converts them to MSI
writes via its integrated I/OxAPIC, or handles them via the legacy 8259 controller.
All root port interrupt sources within the IIO (hot plug, error, power management)
support both MSI mode interrupt delivery and legacy INTx mode interrupt delivery.
Intel
®
QuickData Technology supports MSIX and legacy INTx interrupt deliveries.
Where noted, the root port interrupt sources (except the error source) also support the
ACPI-based mechanism (via GPE messages) for system driver notification. IIO also
supports generation of SMI/PMI/NMI interrupts directly from the IIO to the processor
(bypassing PCH), in support of IIO error reporting. For Intel
®
QPI-defined legacy
virtual message (VLW) signaling, IIO supports an inband VLW interface to the legacy
bridge and an inband interface on Intel
®
QPI. IIO logic handles the conversion between
the two.
7.2 Legacy PCI Interrupt Handling
On PCI Express, interrupts are represented with either MSI-x or inbound interrupt
messages (Assert_INTx/De-assert_INTx). For legacy interrupts, the integrated
I/OxAPIC in IIO converts the legacy interrupt messages from PCI Express to MSI
interrupts. If the I/OxAPIC is disabled (via the mask bits in the I/OxAPIC table entries),
then the messages are routed to the legacy PCH. The subsequent paragraphs describe
how IIO handles this INTx message flow, from its PCI Express ports and internal
devices.
The IIO (both legacy and non-legacy) tracks the assert/de-assert messages for each of
the four interrupts INTA, INTB, INTC, INTD from each PCI Express port (including when
configured as NTB) and Intel
®
QuickData Technology DMA. Each of these interrupts
from each root port is routed to a specific I/OxAPIC table entry (see Table 108 for the
mapping) in that IIO. If the I/OxAPIC entry is masked (via the ‘mask’ bit in the
corresponding Redirection Table Entry), then the corresponding PCI Express
interrupt(s) is forwarded to the legacy PCH, as controlled by the mask bit in the
Redirection Table, provided the ‘Disable PCI INTx Routing to PCH’ bit is clear in the
QPIPINTRC register.
There is a 1:1 correspondence between the message type received from PCI Express
and the message type forwarded to the legacy PCH. For example, if a PCI Express port
INTA message is masked in the integrated I/OxAPIC, then it is forwarded to legacy PCH
as INTA message (subject to the ‘Disable Interrupt Routing to PCH’ bit being clear).