Datasheet

System Address Map
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
338 Order Number: 323103-001
Inbound I/O and configuration transactions from any PCIe port are not supported and
will be master aborted.
6.4.3 Intel
®
VT-d Address Map Implications
Intel
®
VT-d applies only to inbound memory transactions. Inbound I/O and
configuration transactions are not affected by VT-d. Inbound I/O, configuration and
message decode and forwarding happens the same whether VT-d is enabled or not. For
memory transaction decode, the host address map in VT-d corresponds to the address
map discussed earlier in the chapter and all addresses after translation are subject to
the same address map rule checking (and error reporting) as in the non-VT-d mode.
There is not a fixed guest address map that the IIO VT-d hardware can rely upon
(except that the guest domain addresses cannot go beyond the guest address width
specified via the GPA_LIMIT register) i.e. it is OS dependent. IIO converts all incoming
memory guest addresses to host addresses and then applies the same set of memory
address decoding rules as described earlier. In addition to the address map and
decoding rules discussed earlier, the IIO also supports an additional memory range
called the VTBAR range and this range is used to handle accesses to VT-d related
chipset registers. Only aligned DWORD/QWORD accesses are allowed to this region.
Only outbound and SMBus accesses are allowed to this range and also these can only
be accesses outbound from Intel
®
QPI. Inbound accesses to this address range are
completer aborted by the IIO.
§ §
DRAM Memory holes
and other non-existent
regions
• {4G <= Address <= TOHM (OR) 0 <=
Address <= TOLM } AND address does
not decode to any socket in Intel
®
QPI
source decoder
• Address > TOCM
• When VT-d translation enabled, and guest
address greater than 2^GPA_LIMIT
Master Abort
All Else
Forward to subtractive decode
port for legacy Intel
®
Xeon
®
processor C5500/C3500 series.
Aborts locally for non-legacy
Intel
®
Xeon
®
processor C5500/
C3500 series.
1. The VTBAR range would be within the MMIOL range of that IIO. By that token, VTBAR range can never overlap
with any dram ranges.
2. The Intel
®
QuickData Technology DMA BAR and I/OxAPIC MBAR regions of an IIO overlap with MMIOL/MMIOH
ranges of that IIO
3. Intel
®
QuickData Technology DMA does not support generating memory accesses to the VGA memory range
and it will abort all transactions to that address range. Also, if peer-to-peer memory read disable bit is set,
VGA memory reads are aborted
4. If peer-to-peer memory read disable bit is set, then peer-to-peer memory reads are aborted
Table 106. Inbound Memory Address Decoding (Sheet 2 of 2)
Address Range Conditions IIO Behavior