Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 337
System Address Map
6.4.2.2 Summary of Inbound Address Decoding
Table 106, “Inbound Memory Address Decoding” summarizes the IIO behavior on
inbound memory transactions from any PCIe port. This table is only intended to show
the routing of transactions based on the address. It is not intended to show the details
of several control bits that govern forwarding of memory requests from a given PCI
Express port. See the PCI Express Base Specification, Revision 2.0 and the registers
chapter for details of these control bits.
Table 106. Inbound Memory Address Decoding (Sheet 1 of 2)
Address Range Conditions IIO Behavior
DRAM
Address within 0:TOLM or 4GB:TOHM and SAD
hit
Forward to Intel
®
QPI.
Interrupts
Address within FEE00000-FEEFFFFF and write Forward to Intel
®
QPI.
Address within FEE00000-FEEFFFFF and read UR response
HPET, I/OxAPIC, TSeg,
Relocated CSeg, FWH,
VTBAR
1
(when
enabled), Protected
Intel
®
VT-d range Low
and High, Generic
Protected dram range,
Intel
®
QuickData
Technology DMA and I/
OxAPIC BARs
2
FC00000-FEDFFFFF or FEF00000-FFFFFFFF
TOCM >= Address >= TOCM-64GB
•VTBAR
•VT-d_Prot_High
•VT-d_Prot_Low
•Generic_Prot_DRAM
•Intel
®
QuickData Technology DMA BAR
I/OxAPIC ABAR and MBAR
Completer abort
VGA
3
Address within 0A0000h-0BFFFFh and main
switch SAD is programmed to forward VGA
Forward to Intel
®
QPI
Address within 0A0000h-0BFFFFh and main
switch SAD is NOT programmed to forward
VGA and one of the PCIe has VGAEN bit set
Forward to the PCIe port
Address within 0A0000h-0BFFFFh and main
switch SAD is NOT programmed to forward
VGA and none of the PCIe has VGAEN bit set
and DMI port is the subtractive decoding port
Forward to DMI
Address within 0A0000h-0BFFFFh and main
switch SAD is NOT programmed to forward
VGA and none of the PCIe ports have VGAEN
bit set and DMI is not the subtractive decode
port
Master abort
Other peer-to-peer
4
Address within LMMIOL.BASE/LMMIOL.LIMIT or
LMMIOH.BASE/LMMIOH.LIMIT and a PCIE port
positively decoded as target
Forward to the PCI Express port
Address within LMMIOL.BASE/LMMIOL.LIMIT or
LMMIOH.BASE/LMMIOH.LIMIT and no PCIE
port positively decoded as target and DMI is
the subtractive decoding port
Forward to DMI
Address within LMMIOL.BASE/LMMIOL.LIMIT or
LMMIOH.BASE/LMMIOH.LIMIT and no PCIE
port decoded as target and DMI is not the
subtractive decoding port
Master Abort Locally
Address NOT within LMMIOL.BASE/
LMMIOL.LIMIT or LMMIOH.BASE/LIOH.LIMIT,
but is within GMMIOL.BASE/GMMIOL.LIMIT or
GMMIOH.BASE/GMMIOH.LIMIT
Forward to Intel
®
QPI