Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 335
System Address Map
6.4.2 Inbound Address Decoding
This section covers the decoding that is done on any transaction that is received on a
PCIE or DMI port or any transaction that originates from the Intel
®
QuickData
Technology DMA port.
6.4.2.1 Overview
• All inbound addresses that fall above the top of Intel
®
QPI physical address limit
are flagged as errors by the IIO. Top of Intel
®
QPI physical address limit is
dependent on the Intel
®
QPI profile. Register IIOMISCCTRL: IIO MISC Control
defines the top-of- Intel
®
QPI-physical memory.
• Inbound decoding towards main memory in the IIO happens in two steps. The first
step involves a ‘coarse decode’ towards main memory using two separate system
memory window ranges (0-TOLM, 4 GB-TOHM) that can be setup by software.
These ranges are non-overlapping. The second step is the fine source decode
towards an individual socket using the Intel
®
QPI memory source address
decoders.
— A sub-region within one of the two coarse regions can be marked as non-
coherent.
— VGA memory address would overlap one of the two main memory ranges and
IIO decoder is cognizant of that and steers these addresses towards the VGA
device of the system.
• Inbound peer-to-peer decoding also happens in two steps. The first step involves
decoding peer-to-peer crossing Intel
®
QPI (remote peer-to-peer) and peer-to-peer
not crossing Intel
®
QPI (local peer-to-peer). See Figure 65, “Intel® Xeon®
Processor C5500/C3500 Series Only: Peer-to-Peer Illustration” on page 336 for
illustration of remote peer-to-peer.The second step involves actual target decoding
for local peer-to-peer (if transaction targets another device south of the IIO) and
also involves source decoding using Intel
®
QPI source address decoders for remote
peer-to-peer.
— A pair of base/limit registers are provided for the IIO to positively decode local
peer-to-peer transactions. Another pair of base/limit registers are provided that
covers the global peer-to-peer address range (i.e. peer-to-peer address range
of the entire system). Any inbound address that falls outside of the local peer-
to-peer address range but that falls within the global peer-to-peer address
range is considered as a remote peer-to-peer address.
— Fixed VGA memory addresses (A0000-BFFFF) are always peer-to-peer
addresses and would reside outside of the global peer-to-peer memory address
ranges mentioned above. The VGA memory addresses also overlap one of the
system memory address regions, but the IIO always treats the VGA addresses
as peer-to-peer addresses. VGA I/O addresses (3B0h-3BBh, 3C0h-3DFh)
always are forwarded to the VGA I/O agent of the system. The IIO performs
only 16-bit VGA I/O address decode inbound.
— Subtractively decoded inbound addresses are forwarded to the subtractive
decode port of the IIO.
• Inbound accesses to I/OxAPIC, FWH, and Intel
®
QuickData Technology DMA BAR,
are blocked by the IIO (completer aborted).