Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 333
System Address Map
6.4.1.6 Summary of Outbound Memory/IO/Configuration Decoding
Throughout the tables in this section, a reference to a PCIe port generically refers to a
standard PCIe port or a DMI port.
Note: Intel
®
Xeon
®
processor C5500/C3500 series will support configurations cycles that
originate only from the CPU. For Intel
®
Xeon
®
processor C5500/C3500 series’s NTB,
inbound CFG is support for access to the Secondary configuration registers.
Table 103. Decoding of Outbound Memory Requests from Intel
®
QPI (from CPU or
Remote Peer-to-Peer)
Address
Range
Conditions
1
1. See description before this table for clarification of what is actually described in the table
IIO Behavior
Intel
®
QuickData
Technology
DMA BAR, I/
OxAPIC BAR,
ABAR, VTBAR
CB_BAR, ABAR, MBAR, VTBAR and remote p2p
access
Completer Abort
CB_BAR, ABAR, MBAR, VTBAR and not remote p2p
access
Forward to that target
All other
memory
accesses
Not (CB_BAR, ABAR, MBAR, VTBAR, TPM) and one of
the downstream ports
2
positively claimed the
address
2. For this table, NTB is considered to be one of the ‘downstream ports’.
Forward to that port
Not (CB_BAR, ABAR, MBAR, VTBAR, TPM) and none
of the downstream ports positively claimed the
address and DMI is the subtractive decode port
Forward to DMI (legacy Intel
®
Xeon
®
processor C5500/C3500 series)
Not (CB_BAR, ABAR, MBAR, VTBAR, TPM) and none
of the downstream ports positively claimed the
address and DMI is not the subtractive decode port
Master Abort locally (non-legacy
Intel
®
Xeon
®
processor C5500/C3500
series)