Datasheet

System Address Map
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
332 Order Number: 323103-001
Table 102. Outbound Target Decoder Entries
Address Region
Target
Decoder
Entry
Comments
VGA (Memory space
0xA_0000 - 0xB_FFFF and IO
space 0x3B0 - 0x3BB and
0x3C0 - 0x3DF)
4+1
1
1. This is listed as 4+1 entries because each of the four (or five of non-legacy IIO) local P2P bridges have their
own VGA decode enable bit and local IIO has to comprehend this bit individually for each port, and local IIO
QPIPVGASAD.Valid bit is used to indicate the dual IIO has VGA port or not.
Fixed.
TPM/LT/FW ranges (E/F segs
and 4G-16M to 4G)
1
Fixed.
MMIOL
4
Variable. From P2P Bridge Configuration Register Space
I/OxAPIC
4
Variable. From P2P Bridge Configuration Register Space
MMIOH
4
Variable. From P2P Bridge Configuration Register Space
(upper 32 bits PM BASE/LIMIT)
CFGBUS
1
Legacy IIO internal bus number should be set to bus 0.
4
Variable. From P2P Bridge Configuration Register Space for
PCIe bus number decode.
Intel
®
QuickData Technology
DMA
8
Variable. Intel
®
QuickData Technology DMA BAR
VTBAR
1
Variable. Decodes the VT-d chipset registers.
ABAR
1
Variable. Decodes the sub-region within FEC address range
for the integrated I/OxAPIC in the IIO.
MBAR
1
Variable. Decodes any 32-bit base address for the
integrated I/OxAPIC in the IIO.
IO
4
Variable. From four local P2P Bridge Configuration Register
Space of the PCIE port.