Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 331
System Address Map
6.4.1.2 FWH Decoding
FWH accesses are allowed only from a CPU. Accesses from SMBus or PCIe are not
supported. All FWH addresses (4 GB:4 GB-16 MB) and (1 MB:1 MB-128 K) that do not
positively decode to the IIO’s PCIe ports, are subtractively forwarded to its legacy
decode port.
When the IIO receives a transaction from QPI within 4 GB:4 GB-16 MB or 1 MB:1 MB-
128 K and there is no positive decode hit against any of the other valid targets (if there
is a positive decode hit to any of the other valid targets, the transaction is sent to that
target), then the transaction is forwarded to DMI.
6.4.1.3 I/OxAPIC Decoding
I/OxAPIC accesses are allowed only from the Intel
®
QPI. The IIO provides an I/OxAPIC
base/limit register per PCIe port for decoding to I/OxAPIC in downstream components
like PXH. The integrated I/OxAPIC in the IIO decodes two separate base address
registers both targeting the same I/OxAPIC memory mapped registers. Decoding flow
for transactions targeting I/OxAPIC addresses is the same as for any other memory-
mapped IO registers on PCIe.
6.4.1.4 Other Outbound Target Decoding
Other address ranges (besides CSR, FWH, I/OxAPIC) that need to be decoded per
PCIe/DMI port include the standard P2P bridge decode ranges (mmiol, mmioh, i/o, vga,
config). See the PCI-PCI Bridge 1.2 Specification and PCI Express Base Specification,
Revision 1.1 for details. These ranges are also summarized in Table 102, “Outbound
Target Decoder Entries” below.
•Intel
®
QuickData Technology DMA memory BAR
— Remote peer-to-peer accesses from Intel
®
QPI that target Intel
®
QuickData
Technology DMA BAR region are not completer aborted by the IIO. If inbound
protection is needed, VTd translation table should be used to protect at the
source IIO. If the VTd table is not enabled, a Generic Protected Memory Range
could be used to protect. A last defense is to turn off IB P2P MMIO via new bits
in the IIOMISCCTRL register.
6.4.1.5 Summary of Outbound Target Decoder Entries
Table 102, “Outbound Target Decoder Entries” provides a list of all the target decoder
entries in the IIO, such as PCIe port, required by the outbound target decoder to
positively decode towards a target
.