Datasheet
System Address Map
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
330 Order Number: 323103-001
non legacy IIO, the Intel
®
QPI port is the subtractive decode port. Thus all
subtractively decoded transactions will eventually target the PCH.
— The SUBDECEN bit in the IIO Miscellaneous Control Register (IIOMISCCTRL)
sets the subtractive port of the IIO.
— Virtual peer-to-peer bridge decoding related registers with their associated
control bits (e.g. VGAEN bit) and other miscellaneous address ranges (I/
OxAPIC) of a DMI port are NOT valid (and ignored by the IIO decoder) when
they are set as the subtractive decoding port. Subtractive decode transactions
are forwarded to the legacy DMI port, irrespective of the setting of the MSE/
IOSE bits in that port.
• Unless specified otherwise, all addresses are first positively decoded against all
target address ranges. Valid targets are PCIe, DMI, Intel
®
QuickData Technology
DMA, and I/OxAPIC . Beside the standard peer-to-peer decode ranges (refer to the
PCI-PCI Bridge 1.2 Specification for details) for PCIe ports, the target addresses for
these ports also include the I/OxAPIC address ranges. Software has the
responsibility to make sure that only one target can ultimately be the target of a
given address and the IIO will forward the transaction towards that target
.
— For outbound transactions, when no target is positively decoded, the
transactions are sent to the downstream DMI port if it is indicated as the
subtractive decode port. In the Intel
®
Xeon
®
processor C5500/C3500 series, if
DMI is not the subtractive decode port as in a non-legacy Intel
®
Xeon
®
processor C5500/C3500 series, the transaction is master aborted.
— For inbound transactions on a legacy Intel
®
Xeon
®
processor C5500/C3500
series, when no target is positively decoded, the transactions are sent to DMI.
In a non-legacy Intel
®
Xeon
®
processor C5500/C3500 series, when no target is
positively decoded, the transactions are sent to the Intel
®
QPI and eventually
to the DMI port on the legacy IIO.
• For positive decoding, the memory decode to each PCIE target is governed by
Memory Space Enable (MSE) bit in the device PCI configuration space and I/O
decode is covered by the I/O Space Enable bit in the device PCI configuration
space. The only exceptions to this rule are the per port (external) I/OxAPIC address
range and the internal I/OxAPIC ABAR address range which are decoded
irrespective of the setting of the memory space enable bit. There is no decode
enable bit for configuration cycle decoding towards either a PCIe port or the
internal CSR configuration space of the IIO.
• The target decoding for internal VTdCSR space is based on whether the incoming
CSR address is within the VTdCSR range (limit is 8K plus the base, VTBAR).
• Each PCIE/DMI port in the IIO has one special address range - I/OxAPIC.
• No loopback supported i.e. a transaction originating from a port is never sent back
to the same port and the decode ranges of originating port are ignored in address
decode calculations.