Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 33
Features Summary
1.9 Related Documents
See the following documents for additional information. Unless otherwise noted, obtain
the documents from http://www.intel.com.
PCH
Platform Controller Hub. The new, 2009 chipset with centralized platform
capabilities including the main I/O interfaces along with display connectivity,
audio features, power management, manageability, security and storage
features. The PCH may also be referred to by the name Intel
®
3420 chipset.
PECI Platform Environment Control Interface
Processor The 64-bit, single-core or multi-core component (package)
Processor Core
The term “processor core” refers to a processing element containing an
execution unit with its own instruction cache, data cache, and MLC. A die may
contain one or more cores, all sharing one common LLC.
Rank
A unit of DRAM composed of and adequate number of memory chips in parallel
so as to provide 64 bits of data or 72 bits data + ECC. These devices are usually
mounted on a single side of a DIMM.
Resilvering
The process of re-synchronizing a memory channel that experienced an
uncorrectable ECC error in a system utilizing mirroring of memory channels.
SAD Source Address Decoder
SCI System Control Interrupt. Used in ACPI protocol.
SMT Simultaneous Multi-Threading.
SS engine Sparing/Scrub engine
Storage Conditions
A non-operational state. The processor may be installed in a platform, in a tray,
or loose. Processors may be sealed in packaging or exposed to free air. Under
these conditions, processor landings should not be connected to any supply
voltages, have any I/Os biased or receive any clocks. Upon exposure to “free air”
(i.e., unsealed packaging or a device removed from packaging material) the
processor must be handled in accordance with moisture sensitivity labeling
(MSL) as indicated on the packaging material.
TAC Thermal Averaging Constant
TDP Thermal Design Power
TOM Top of Memory
TTM Time-To-Market
UP Uni-processor
x1 Refers to a Link or Port with one Physical Lane
x4 Refers to a Link or Port with four Physical Lanes
x8 Refers to a Link or Port with eight Physical Lanes
x16 Refers to a Link or Port with sixteen Physical Lanes
Table 2. Terminology (Sheet 2 of 2)
Term Description
Table 3. Processor Documents
Document Document Number
Intel
®
Xeon
®
Processor C5500/C3500 Series and LGA1366 Socket Thermal
Mechanical Design Guide
323107
Voltage Regulator Module (VRM) and Enterprise Voltgage Regulator Down
(EVRD) 11.1 Design Guidelines, Revision 1.5
397898