Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 329
System Address Map
6.3 IIO Address Map Notes
6.3.1 Memory Recovery
When software recovers an underlying DRAM memory region that resides below the
4 GB address line that is used for system resources like firmware, local APIC, and
IOAPIC, etc. (the gap below 4 GB address line), it needs to make sure that it does not
create system memory holes whereby all the system memory cannot be decoded with
two contiguous ranges. It is OK to have unpopulated addresses within these contiguous
ranges that are not claimed by any system resource. The IIO decodes all inbound
accesses to system memory via two contiguous address ranges (0-TOLM, 4GB-TOHM)
and there cannot be holes created inside of those ranges that are allocated to other
system resources in the gap below 4GB address line. The only exception to this is the
hole created in the low system DRAM memory range via the VGA memory address. The
IIO comprehends this and does not forward these VGA memory regions to system
memory.
6.3.2 Non-Coherent Address Space
The IIO supports one coarse main memory range which can be treated as non-coherent
by the IIO, i.e. inbound accesses to this region are treated as non-coherent. This
address range has to be a subset of one of the coarse memory ranges that the IIO
decodes towards system memory. Inbound accesses to the NC range are not snooped.
6.4 IIO Address Decoding
In general, software needs to guarantee that for a given address there can only be a
single target in the system. Otherwise, it is a programming error and results are
undefined. The one exception is that VGA addresses would fall within the inbound
coarse decode memory range. The IIO inbound address decoder handles this conflict
and forwards the VGA addresses to only the VGA port in the system (and not system
memory).
6.4.1 Outbound Address Decoding
This section covers address decoding that the IIO performs on a transaction from the
Intel
®
QPI that targets one of the downstream devices/ports of the IIO. In the
description in the rest of the section, PCIe refers to all of a standard PCI Express port
and DMI, unless noted otherwise.
6.4.1.1 General Overview
• Before any transaction from the Intel
®
QPI is decoded by the IIO, the NodeID in
the incoming transaction must match the NodeIDs assigned to the IIO (any
exceptions are noted when required). Else it is an error. See Chapter 11.0, “IIO
Errors Handling Summary,” for details of error handling.
• All target decoding toward PCIe, firmware and internal IIO devices follow address
based routing. Address based routing follows the standard PCI tree hierarchy
routing.
• NodeID based routing is not supported downstream of the Intel
®
QPI port in the
IIO.
• The subtractive decode port in the IIO is the port that is a) the recipient of all
addresses that are not positively decoded towards any of the valid targets in the
IIO and b) the recipient of all message/special cycles that are targeted at the
legacy PCH. For the legacy IIO, the DMI port is the subtractive decode port. For the