Datasheet

System Address Map
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
328 Order Number: 323103-001
6.2 IO Address Space
There are four classes of I/O addresses that are specifically decoded by the platform:
• I/O addresses used for VGA controllers.
• I/O addresses used for ISA aliasing.
• I/O addresses used for the PCI Configuration protocol - CFC/CF8.
• I/O addresses used by downstream PCI/PCIE IO devices, typically legacy devices.
This space is divided amongst the IIOs in the system. Each IIO can be associated
with an IO range. The range can be further divided by various downstream ports in
the IIO. Each downstream port in the IIO contains a BAR to decode its IO range.
Address that falls within this range is forwarded to its respective IIO, then
subsequently to the downstream port in the IIO.
6.2.1 VGA I/O Addresses
Legacy VGA device uses up the addresses 3B0h-3BBh, 3C0h-3DFh. Any PCIe, DMI port
in the IIO can be a valid target of these address ranges if the VGAEN bit in the P2P
bridge control register corresponding to that port is set (besides the condition where
these regions are positively decoded within the P2P I/O address range). In the
outbound direction at the PCI-2-PCI bridge (part of PCIe port) direction, by default, the
IIO only decodes the bottom 10 bits of the 16-bit I/O address when decoding this VGA
address range with the VGAEN bit set in the P2P bridge control register. But when the
VGA16DECEN bit is set in addition to VGAEN being set, the IIO performs a full 16-bit
decode for that port when decoding the VGA address range outbound. .
Note: For an Intel
®
Xeon
®
processor C5500/C3500 series DP configuration, only one of the
four PCIe ports in the legacy Intel
®
Xeon
®
processor C5500/C3500 series may have
the VGAEN bit set.
6.2.2 ISA Addresses
The IIO supports ISA addressing per the PCI-PCI Bridge 1.2 Specification. ISA
addressing is enabled in a PCIe port via the ISAEN bit in the bridge configuration space.
When the VGAEN bit is set in a PCIe port without the VGA16DECEN bit being set, then
the ISAEN bit must be set in all the peer PCIe ports in the system.
6.2.3 CFC/CF8 Addresses
These addresses are used by legacy operating systems to generate PCI configuration
cycles. These have been replaced with a memory-mapped configuration access
mechanism in PCI Express (which only PCI Express aware operating systems utilize).
That said, the IIO does not explicitly decode these I/O addresses and take any specific
action. These accesses are decoded as part of the normal inbound and outbound I/O
transaction flow and follow the same routing rules. See also Table 106, “Inbound
Memory Address Decoding” on page 337 and Table 105, “Subtractive Decoding of
Outbound I/O Requests from Intel® QPI” on page 334 for further details of I/O address
decoding in the IIO.
6.2.4 PCIe Device I/O Addresses
These addresses could be anywhere in the 64 KB I/O space and are used to allocate
I/O addresses to PCIe devices. Each IIO is allocated a chunk of I/O address space and
there are IIO-specific requirements on how these chunks are distributed amongst IIOs.
See Section 6.4.3, “Intel® VT-d Address Map Implications” for details of these
restrictions.