Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 327
System Address Map
6.1.7 Address Regions above 4 GB
6.1.7.1 High System Memory
This region is used to describe the address range of system memory above the 4GB
boundary. The IIO forwards all inbound accesses to this region to DRAM, unless any of
these access addresses are also marked protected. See GENPROTRANGE1.BASE and
GENPROTRANGE2.BASE registers. A portion of the address range within this high
system DRAM region could be marked non-coherent (via NcMem.Base/NcMem.Limit
register) and the IIO treats them as non-coherent. All other addresses are treated as
coherent (unless modified via the NS attributes on PCI Express). The IIO should not
receive outbound accesses to this region, but the IIO does not explicitly check for this
error condition but rather subtractively forwards these accesses to the subtractive
decode port, if one exists downstream.
Software must setup this address range such that any recovered DRAM hole from
below the 4 GB boundary and that might encompass a protected sub-region is not
included in the range.
6.1.7.2 Memory Mapped IO High
The high memory mapped I/O range is located above main memory. This region is used
to map I/O address requirements above 4 GB range. Each IIO in the system is
allocated a portion of this system address region and within that portion each PCIe port
and other integrated IIO devices (Intel
®
QuickData Technology DMA BAR) use up a
sub-range. IIO-specific requirements define how software allocates this system region
amongst IIOs to support of peer-to-peer between IIOs in this address range. See
Section 6.4.3, “Intel® VT-d Address Map Implications” for details of these restrictions.
Each IIO has a couple of MMIIO address range registers (LMMIOH and GMMIOH) to
support local and remote peer-to-peer in the MMIIO address range. See Section 6.4.1,
“Outbound Address Decoding” and Section 6.4.2, “Inbound Address Decoding” for
details of inbound and outbound decoding for accesses to this region.
6.1.8 Protected System DRAM Regions
The IIO supports two address ranges for protecting various system DRAM regions that
carry protected OS code or other proprietary platform information. The ranges are:
•Intel
®
VT-d protected high range
•Intel
®
VT-d protected low range
The IIO provides a 64-bit programmable address window for this purpose. All accesses
that hit this address range are completer aborted by the IIO. This address range can be
placed anywhere in the system address map and could potentially overlap one of the
coarse DRAM decode ranges.
Address Region From To
High System Memory 4 GB TOHM
Address Region From To
MMIIO GMMIIO.Base GMMIIO.Limit