Datasheet
Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 325
System Address Map
6.1.6 Memory Address Range TOLM – 4 GB
6.1.6.1 PCI Express Memory Mapped Configuration Space (PCI MMCFG)
This is the system address region that is allocated for software to access the PCI
Express Configuration Space. This region is relocatable below 4 GB by BIOS/firmware.
6.1.6.2 MMIOL
This region is used for PCIE device memory addressing below 4 GB. Each IIO in the
system is allocated a portion of this address range and individual PCIe ports and other
integrated devices within an IIO (e.g. Intel
®
QuickData Technology DMA BAR, I/OxAPIC
MBAR) use sub-portions within that range. IIO-specific requirements define how
software allocates this system region amongst IIOs to support of peer-to-peer between
IIOs. See Section 6.4.3, “Intel® VT-d Address Map Implications” for details of these
restrictions. Each IIO has a couple of MMIOL address range registers (LMMIOL and
GMMIOL) to support local and remote peer-to-peer in the MMIOL address range. See
Section 6.4, “IIO Address Decoding” for details of how these registers are used in the
inbound and outbound MMIOL range decoding.
6.1.6.3 I/OxAPIC Memory Space
This is a 1 MB range used to map I/OxAPIC Controller registers. The I/OxAPIC spaces
are used to communicate with I/OxAPIC interrupt controllers that are populated in
downstream devices like the PCH and also the IIO’s integrated I/OxAPIC. The range can
be further divided by various downstream ports in the IIO and the integrated I/OxAPIC.
Each downstream port in IIO contains a Base/Limit register pair (APICBase/APICLimit)
to decode its I/OxAPIC range. Addresses that falls within this range are forwarded to
that port. Similarly, the integrated I/OxAPIC decodes its I/OxAPIC base address via the
ABAR register. The range decoded via the ABAR register is a fixed size of 256 B. The
integrated I/OxAPIC also decodes a standard PCI-style 32-bit BAR (located in the PCI
defined BAR region of the PCI header space) that is 4KB in size. It is called the MBAR
and is provided so that the I/OxAPIC can be placed anywhere in the 4 G memory
space.
Only outbound accesses are allowed to this FEC address range and also to the MBAR
region. Inbound accesses to this address range are blocked by the IIO and return a
completer abort response. Outbound accesses to this address range that are not
positively decoded towards any one PCIe port are sent to the subtractive decode port of
the IIO. See section Section 6.4.1, “Outbound Address Decoding” and Section 6.4.2,
“Inbound Address Decoding” for complete details of outbound address decoding to the
I/OxAPIC space.
Accesses to the I/OxAPIC address region (APIC Base/APIC Limit) of each root port, are
decoded by the IIO irrespective of the setting of the MemorySpaceEnable bit in the root
port P2P bridge register.
Address Region From To
MMIOL GMMIOL.Base GMMIOL.Limit
Address Region From To
I/OxAPIC FEC0_0000 FECF_FFFF