Datasheet

System Address Map
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
324 Order Number: 323103-001
6.1.3 Address Region Between 1 MB and TOLM
This region is always allocated to system DRAM memory. Software must set up one of
the coarse memory decode ranges that IIO uses for inbound system memory decoding
to include this address range. The IIO will forward inbound accesses to this region to
system memory (unless any of these access addresses fall within a protected dram
range). It would be an error for IIO to receive outbound accesses to an address in this
region, other than snoop requests from Intel
®
QPI links. However, the IIO does not
explicitly check for this error condition, and simply forwards such accesses to the
subtractive decode port.
Any inbound access that decodes within one of the two coarse memory decode
windows with no physical DRAM populated for that address will result in a master abort
response on PCI Express.
6.1.3.1 Relocatable TSeg
These are system DRAM memory regions that are used for SMM/CMM mode operation.
IIO would completer abort all inbound transactions that target these address ranges.
IIO should not receive transactions that target these addresses in the outbound
direction, but IIO does not explicitly check for this error condition but rather
subtractively forwards such transactions to the subtractive decode port of the IIO, if
one exists downstream.
The location (1 MB aligned) and size (from 512 KB to 8 MB) in IIO can be programmed
by software. This range check by IIO can also be disabled by the TSEG_EN control bit.
6.1.4 PAM Memory Area Details
There are 13 memory regions from 768 KB to 1 MB (0C0000h - 0FFFFFh) which
comprise the PAM Memory Area. These regions can be programmed as Disabled, Read
Only,Write Only and R/W from a DRAM perspective. This region can be used to shadow
the BIOS region to DRAM for faster access. See the processor’s SAD_PAM0123 and
SAD_PAM456 registers for details.
Non-snooped accesses from PCI Express or DMI to this region are always sent to
DRAM.
6.1.5 ISA Hole (15 MB –16 MB)
A hole can be created at 15 MB-16 MB as controlled by the fixed hole enable bit (HEN)
in the processor’s SAD_HEN register. Accesses within this hole are forwarded to the
DMI Interface. The range of physical DRAM memory disabled by opening the hole is not
remapped to the top of the memory – that physical DRAM space is not accessible. This
15 MB-16 MB hole is an optionally enabled ISA hole.
Address Region From To
TSeg FE00_0000 (default) FE7F_FFFF (default)