Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 323
System Address Map
6.1.2.1 VGA/SMM Memory Space
This legacy address range is used by video cards to map a frame buffer or a character-
based video buffer. By default, accesses to this region are forwarded to main memory
by the processor. However, once firmware figures out where the VGA device is in the
system, it sets up the processor’s source address decoders to forward these accesses
to the appropriate IIO. If the VGAEN bit is set in the IIO PCI bridge control register
(BCR) of a PCI Express port, then transactions within the VGA space are forwarded to
the associated port, regardless of the settings of the peer-to-peer memory address
ranges of that port. If none of the PCI Express ports have the VGAEN bit set (per the
IIO address map constraints, the VGA memory addresses cannot be included as part of
the normal peer-to-peer bridge memory apertures in the root ports), then these
accesses are forwarded to the subtractive decode port. See also the PCI-PCI Bridge 1.2
Specification for further details on the VGA decoding. Only one VGA device may be
enabled per system partition. The VGAEN bit in the PCIe bridge control register must be
set only in one PCI Express port in a system partition. The IIO does not support the
MDA (monochrome display adapter) space independent of the VGA space.
Note: For a Intel
®
Xeon
®
processor C5500/C3500 series DP configuration, only one of the
four PCIe ports in the legacy Intel
®
Xeon
®
processor C5500/C3500 series may have
the VGAEN bit set.
The VGA memory address range can also be mapped to system memory in SMM. The
IIO is totally transparent to the workings of this region in the SMM mode. All outbound
and inbound accesses to this address range are always forwarded to the VGA device of
the partition. See Table 106 for further details of inbound and outbound VGA decoding.
6.1.2.2 C/D/E/F Segments
The E/F region could be used to address DRAM from an I/O device (processors have
registers to select between addressing BIOS flash and DRAM). IIO does not explicitly
decode the E/F region in the outbound direction and relies on subtractive decoding to
forward accesses to this region to the legacy PCH. IIO does not explicitly decode
inbound accesses to the E/F address region. It is expected that the DRAM low range
that IIO decodes will be setup to cover the E/F address range. By virtue of that, the IIO
will forward inbound accesses to the E/F segment to system DRAM. If it is necessary to
block inbound access to these ranges, the Generic Memory Protection Ranges could be
used.
C/D region is used in system DRAM memory for BIOS and option ROM shadowing. The
IIO does not explicitly decode these regions for inbound accesses. Software must
program one of the system DRAM memory decode ranges that the IIO uses for inbound
system memory decoding to include these ranges.
All outbound accesses to the C thorough F regions are first positively decoded against
all valid targets’ address ranges and if none match, these address are forwarded to the
subtractive decode port of the IIO, if one exists; else it is an error condition.
The IIO will complete locks to this range, but cannot guarantee atomicity when writes
and reads are mapped to separate destinations by the processor.
Address Region From To
VGA 000_000A_0000 000_000B_FFFF