Datasheet

System Address Map
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
322 Order Number: 323103-001
6.1.1 System DRAM Memory Regions
These address ranges are always mapped to system DRAM memory, regardless of the
system configuration. The top of main memory below 4 G is defined by the Top of Low
Memory (TOLM). Memory between 4 GB and TOHM is extended system memory. Since
the platform may contain multiple processors, the memory space is divided amongst
the CPUs. There may be memory holes between each processor’s memory regions.
These system memory regions are either coherent or non-coherent. A set of range
registers in the IIO define a non-coherent memory region (NcMem.Base/NcMem.Limit)
within the system DRAM memory region shown above. System DRAM memory region
outside of this range but within the DRAM region shown in table above is considered
coherent.
For inbound transactions, the IIO positively decodes these ranges via a couple of
software programmable range registers. For outbound transactions, it would be an
error for IIO to receive non-coherent accesses to these addresses from Intel
®
QPI.
However, the IIO does not explicitly check for this error condition and simply forwards
such accesses to the subtractive decode port, if one exists downstream, by virtue of
subtractive decoding.
6.1.2 VGA/SMM and Legacy C/D/E/F Regions
Figure 64 shows the memory address regions below 1 MB. These regions are legacy
access ranges.
Address Region From To
640KB DOS Memory 000_0000_0000 000_0009_FFFF
1MB to Top-of-low-memory 000_0010_0000 TOLM
Bottom-of-high-memory to
Top-of-high-memory
4 GB TOHM
Figure 64. VGA/SMM and Legacy C/D/E/F Regions
BIOS Shadow RAM
Accesses controlled at
16K granularity in the
processor source decode
Controlled by VGA Enable
and SMM Enable in the
processor
1MB
640
KB
768
KB
0C
0000
h
0A 0000h
VGA
/
SMM
Regions
0B
8000
h
0B
0000
h
736
KB
704
KB
Key
=
System
Memory
(DOS)
=Low BIOS
=VGA/SMM