Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 321
System Address Map
6.1 Memory Address Space
Figure 63 shows the system memory address space. There are three basic regions of
memory address space in the system: address below 1 MB, address between 1 MB and
4 GB, and address above 4 GB. These regions are described in the following sections.
Throughout this section, there will be references to the subtractive decode port. It
refers to the port of the IIO that is attached to the PCH or provides a path towards the
PCH. This port is also the recipient of all addresses that are not positively decoded
towards any PCI Express device or towards memory.
Figure 63. System Address Map
16MB
1MB
1MB
1MB
64 MB –
256 MB
0
A_0000
C_0000
E_0000
1 MB
Areas are
not
drawn to scale.
DOS
128 K
C and D
Segments
PAM
Region
VGA/SMM
Memory
Range
128 K
640 K
128 K
F_FFFF
4 GB
E and F
Segments
PAM
FWH
LocalxAPIC
LegacyLT/TPM
I/OxAPIC
MMIOL
(relocatable)
FF00_0000
FEE0_0000
FED0_0000
FEC0_0000
TOLM
10_0000
DRAM
High
Memory
Compatibility
Area
Low
Memory
High
Memory
(relocatable)
N X 64 MB
1_0000_0000
TSeg
(programmable)
DRAM
Low
Memory
TOHM
TOCM
TOCM
2^40
12MB
FE00_0000
MMIOH
PCI
MMCFG
Relocatable
N X
64 MB
2^40
FEF0_0000
Rsvd
Reserved
1MB
Reserved
DRAM
Low
Memory
512 KB –
8 MB
variable
variable