Datasheet

System Address Map
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
320 Order Number: 323103-001
6.0 System Address Map
This chapter provides a basic overview of the system address map and describes how
the IIO comprehends and decodes the various regions in the system address map. The
term “IIO” in this chapter refers to the integrated IO module of Intel
®
Xeon
®
processor
C5500/C3500 series. This chapter does not provide the full details of the platform
system address space as viewed by software and it also does not provide the details of
processor address decoding.
The Intel
®
Xeon
®
processor C5500/C3500 series supports 40 bits [39:0] of memory
addressing on its Intel
®
QPI interface. The IIO also supports receiving and decoding 64
bits of address from PCI Express. Memory transactions received from PCI Express that
go above the top of physical address space supported on Intel
®
QPI (which is
dependent on the Intel
®
QPI profile but is always equal to 2^40 for the IIO) are
reported as errors by IIO. The IIO as a requester would never generate requests on PCI
Express with any of address bits 63 to 40 set. For packets the IIO receives from Intel
®
QPI and for packets the IIO receives from PCI Express that fall below the top of Intel
®
QPI physical address space, the upper address bits from top of Intel
®
QPI physical
address space up to bit 63 must be considered as 0s for target address decoding
purposes. The IIO always performs full 64-bit target address decoding.
The IIO supports 16 bits of I/O addressing on its Intel
®
QPI interface. The IIO as a
requester would never generate I/O requests on PCI Express with any of address bits
31 to 16 set.
The IIO supports PCI configuration addressing up to 256 buses, 32 devices per bus and
eight functions per device. A single grouping of 256 buses, 32 devices per bus and
eight functions per device is referred to as a PCI segment. The processor source
decoder supports multiple PCI segments in the system. However, all configuration
addressing within an IIO and hierarchies below an IIO must be within one segment.
The IIO does not support being in multiple PCI segments.