Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 319
IIO Ordering Model
5.6 Configuration Register Ordering Rules
The IIO implements legacy PCI configuration space registers. Legacy PCI configuration
registers are accessed with NcCfgRd and NcCfgWr transactions (using PCI Bus, Device
Function) received on the Intel
®
QPI interface.
For PCI configuration space, the ordering requirements are the same as standard, non-
posted configuration cycles on PCI. See Section 5.2.1 and Section 5.3.1 for details.
Furthermore, on configuration writes to the IIO the completion is returned by the IIO
only after the data is actually written into the register.
5.7 Intel
®
VT-d Ordering Exceptions
The transaction flow to support the address remapping feature of Intel
®
VT-d requires
that the IIO reads from an address translation table stored in memory. This table read
has the added ordering requirement that it must be able to pass all other inbound non-
posted requests (including non-table reads). If not for this bypassing requirement,
there would be an ordering dependence on peer-to-peer reads resulting in a deadlock.
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