Datasheet

IIO Ordering Model
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
318 Order Number: 323103-001
5.4.3 Remote Peer-to-Peer
In the initiating IIO, a remote peer-to-peer transaction follows the same ordering rules
as inbound transactions destined to main memory. In the target IIO, a remote peer-to-
peer transaction follows the same ordering rules as outbound transactions destined to
an I/O device.
RULE 1: Similar to peer to peer write requests, the IIO must serialize remote peer-to-
peer read completions.
5.5 Interrupt Ordering Rules
IOxAPIC or MSI interrupts are either directed to a single processor or broadcast to
multiple processors (see Interrupt chapter for more details). The IIO treats interrupts
as posted transactions with exceptions (Section 5.5.1). This enforces that the interrupt
will not be observed until after all prior inbound writes are flushed to their destinations.
For broadcast interrupts, order-dependent transactions received after the interrupt
must wait until all interrupt completions are received by the IIO.
Since interrupts are treated as posted transactions, the ordering rule that read
completions push interrupts naturally applies as well. For example:
• An interrupt generated by a PCI Express interface must be strongly ordered with
read completions from configuration registers within that same PCI Express root
port.
• Read completions from the integrated IOAPIC’s registers (configuration and
memory-mapped I/O space) must push all interrupts generated by the integrated
IOAPIC.
• Read completions from the Intel
®
VT-d registers must push all interrupts generated
by the Intel
®
VT-d logic (e.g. an error condition).
Similarly, MSIs generated by the IIO internal devices, such as the DMA engine, root
ports, and I/OxAPIC, also need to follow the ordering rules of posted writes. For
example, an interrupt generated by the DMA engine must be ordered with read
completions from the DMA engine registers.
5.5.1 SpcEOI Ordering
When a processor receives an interrupt, it will process the interrupt routine. The
processor will then clear the I/O card’s interrupt by writing to that I/O device’s register.
Finally, for level-triggered interrupts, the processor sends an End-of-Interrupt (EOI)
special cycle to clear the interrupt in the IOxAPIC.
The EOI special cycle is treated as an outbound posted transaction with regard to
ordering rules.
5.5.2 SpcINTA Ordering
The legacy 8259 controller can interrupt a processor through a virtual INTR pin (virtual
legacy wire). The processor responds to the interrupt by sending an interrupt
acknowledge transaction reading the interrupt vector from the 8259 controller. After
reading the vector, the processor will jump to the interrupt routine.
Intel
®
QPI implements an IntAck message to read the interrupt vector from the 8259
controller. With respect to ordering rules, a Intr_Ack message (always outbound) is
treated as a posted request. The completion returns to the IIO on DMI as an
Intr_Ack_Reply (also posted). The IIO translates this into a completion for the Intel
®
QPI Intr_Ack message.