Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 317
IIO Ordering Model
5.4 Peer-to-Peer Ordering Rules
The IIO supports peer-to-peer read and write transactions. A peer-to-peer transaction
is defined as a transaction issued on one PCI Express interface destined for another PCI
Express interface (Note: PCI Express to DMI is also supported). All peer-to-peer
transactions are treated as non-coherent by the system. There are three types of peer-
to-peer transactions supported by the IIO:
Hinted PCI Peer-to-PeerA transaction initiated on a PCI bus destined for another PCI bus
on the same I/O device (i.e., not visible to the IIO). For
example, a PXH (dual-PCI to PCI Express bridge).
Local Peer-to-Peer A transaction initiated on a PCI Express port destined for
another PCI Express port on the same IIO.
Remote Peer-to-Peer A transaction initiated on a PCI Express port of the local IIO
destined for another PCI Express port on the remote IIO
connected via an Intel
®
QPI port.
Local and remote peer-to-peer transactions adhere to the ordering rules listed in
Section 5.2.1 and Section 5.3.1.
5.4.1 Hinted Peer-to-Peer
There are no specific IIO requirements for hinted peer-to-peer since PCI ordering is
maintained on each PCI Express port.
5.4.2 Local Peer-to-Peer
Local peer-to-peer transactions flow through the same inbound ordering logic as
inbound memory transactions from the same PCI Express port. This provides a
serialization point for proper ordering.
When the inbound ordering logic receives a peer-to-peer transaction, the ordering rules
require that it must wait until all prior inbound writes from the same PCI Express port
are completed on the internal Coherent IIO interface. Local peer-to-peer write
transactions complete when the outbound ordering logic for the target PCI Express port
receives the transaction and ordering rules are satisfied. Local peer-to-peer read
transactions are completed by the target device.
Table 101. Outbound Data Flow Ordering Rules
Row Pass Column?
Outbound
Write or
Message
Request
Outbound
Read
Request
Outbound
Configuration
Write Request
Inbound
Read
Completion
Outbound Write or Message Request No
1
1. A Memory Write or Message Request may not pass any other Memory Write or Message Request. The IIO
does not support setting the Relaxed Ordering Attribute bit for an Outbound Memory Write or Message
Request.
Yes Yes Yes
Outbound Read Request No No No Yes
Outbound Configuration or I/O Write
Request
No No No Yes
Inbound Read Completion No Yes Yes
1. Yes
2
2. No
3
2. Inbound read completions from PCIe that have different Tags may not return in the original request order.
3. Multiple sub-completions of a given inbound read request (i.e., with the same Tag) will be returned in address
order. All inbound read completions to DMI are returned by the IIO in the original request order.