Datasheet

IIO Ordering Model
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
316 Order Number: 323103-001
RULE 1: Inbound non-posted completions must be allowed to progress past stalled
outbound non-posted requests.
RULE 2: Outbound posted requests must be allowed to progress past stalled
outbound non-posted requests. This rule prevents deadlocks by
guaranteeing forward progress. Consider the case when the outbound
queues are entirely filled with read requests and likewise, the inbound
queues are also filled with read requests. The only way to prevent the
deadlock is if one of the queues allow completions to flow “around” the
stalled read requests.Consider the example in Rule 1. If the reads are
enqueued and a write transaction is also behind one or more read requests,
the only way for the read completion to proceed is if the prior posted writes
are also allowed to proceed.
RULE 3: Outbound non-posted requests and inbound completions cannot pass
enqueued outbound posted requests.
The producer-consumer model prevents read requests, write requests, and read
completions from passing write requests. See the PCI Local Bus Specification,
Revision 2.3 for details on the producer-consumer ordering model.
RULE 4: If a non-posted inbound request requires multiple sub-completions, those
sub-completions must be delivered on PCI Express in linearly addressing
order.
This rule is a requirement of the PCI Express protocol. For example, if the IIO receives
a request for 4 KB on the PCI Express interface and this request targets the Intel
®
QPI
port (main memory), then the IIO splits up the request into multiple 64 B requests.
Since Intel
®
QPI is an unordered domain, it is possible that the IIO receives the second
cache line of data before the first. Under such unordered situations, the IIO must buffer
the second cache line until the first one is received and forwarded to the PCI Express
requester.
RULE 5: If a configuration write transaction targets the IIO, the completion must not
be returned to the requester until after the write has actually occurred to the
register.
Writes to configuration registers could have side-effects and the requester expects that
it has taken effect prior to receiving the completion for that write. Therefore, the IIO
will not respond to the configuration write until after the register is actually written and
all expected side-effects have completed.
5.3.2 Outbound Ordering Rules Summary
Table 100 indicates an ordering relationship between two outbound transactions as
implemented in the IIO and summarizes the outbound ordering rules described in
previous sections.
Yes The second transaction (row) must be allowed to pass the first (column) to
avoid deadlock per the PCI Express Base Specification, Revision 2.0 or may be
the implementation choice for the IIO (i.e., this entry is Y/N in the PCI Express
Base Specification, Revision 2.0).
No The second transaction must not be allowed to pass the first transaction. This
is may be required to satisfy the Producer-Consumer strong ordering model or
may be the implementation choice for the IIO (i.e., this entry is Y/N in the PCI
Express Base Specification, Revision 2.0).