Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 315
IIO Ordering Model
5.2.3 Inbound Ordering Rules Summary
Table 100 indicates an ordering relationship between two inbound transactions as
implemented in the IIO and summarizes the inbound ordering rules described in
previous sections.
Yes The second transaction (row) allowed to pass the first (column).
No The second transaction not be allowed to pass the first transaction. This is may
be required to satisfy the Producer-Consumer strong ordering model or may
be the implementation choice for the IIO. The first transaction is considered
done when it is globally observed.
Relaxed Ordering (RO) Attribute bit set (1b) means that the RO bit is set in the
transaction and for VC0, IIOMISCCTRL.18 (Disable inbound RO for VC0 traffic) is clear.
Otherwise, relaxed ordering is not enabled.
5.3 Outbound Ordering Rules
Outbound transactions through the IIO are memory, I/O or configuration read/write
transactions originating on an Intel
®
QPI interface destined for a PCI Express or DMI
device. Subsequent outbound transactions with different destinations have no ordering
requirements between them. Multiple transactions destined for the same outbound port
are ordered according to the ordering rules specified in PCI Express Base Specification,
Revision 2.0.
Note: On Intel
®
QPI, non-coherent writes are not considered complete until the IIO returns a
Cmp for the NcWr transaction. On PCI Express and DMI interfaces, memory writes are
posted. Therefore, the IIO should return this completion as soon as possible once the
write is guaranteed to meet the PCI Express ordering rules and is part of the “ordered
domain”. For outbound writes that are non-posted in the PCI Express domain (e.g. I/O
and configuration writes), the target device will post the completion.
5.3.1 Outbound Ordering Requirements
There are no ordering requirements between outbound transactions targeting different
outbound interfaces. For deadlock avoidance, the following rules must be ensured for
outbound transactions targeting the same outbound interface:
Table 100. Inbound Data Flow Ordering Rules
Row Pass Column?
Inbound
Write or
Message
Request
Inbound
Read
Request
Outbound
Read
Completion
Outbound
Configuration
or I/O Write
Completion
Inbound Write or Message Request
1. No
1
2. Yes
2
1. A Memory Write or Message Request with the Relaxed Ordering Attribute bit cleared (0b) may not pass any
other Memory Write or Message Request. If the IIOMISCCTRL.14 (Pipeline NS writes) is set, than the IIO will
pipeline writes and will rely on the platform to maintain this strict ordering.
2. A Memory Write or Message Request with the Relaxed Ordering Attribute bit set (1b) may pass any other
Memory Write or Message Request.
Yes Yes Yes
Inbound Read Request No No Yes Yes
Outbound Read Completion No Yes
1. Yes
3
2. No
4
3. Outbound read completions from PCIe that have different tags may not return in the original request order.
4. Multiple sub-completions of a given outbound read request (i.e., with the same tag) will be returned in
address order. All outbound read completions from DMI are returned in the original request order.
No
Outbound Configuration or I/O Write
Completion
No Yes No No