Datasheet
IIO Ordering Model
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
314 Order Number: 323103-001
RULE 7: If an inbound read completes with multiple sub-completions (e.g. a
cacheline at a time), those sub-completions must be returned on PCI
Express in linearly increasing address order.
The above rules apply whether the transaction is coherent or non-coherent. Some
regions of memory space are considered non-coherent (e.g. the No Snoop attribute is
set). The IIO will order all transactions regardless of its destination.
RULE 8: For PCI Express ports, different read requests should be completed without
any ordering dependency. For the DMI interface, however, all read requests
with the same Tag must be completed in the order that the respective
requests were issued, but, as a simplification, the IIO will return all
completions in original read request order (e.g., independent of whether or
not the requests have the same tag).
Different read requests issued on a PCI Express interface should be completed in any
order. This attribute yields lower read latency for platforms such as Intel
®
Xeon
®
processor C5500/C3500 series in which Intel
®
QPI is an unordered, multipath
interface. However the read completion ordering restriction on DMI implies that the IIO
must guarantee stronger ordering on that interface.
5.2.2 Special Ordering Relaxations
The PCI Express Base Specification, Revision 2.0 specifies that reads do not have any
ordering constraints with other reads. An example of why a read would be blocked is
the case of an Intel
®
QPI address conflict. Under such a blocking condition, subsequent
transactions should be allowed to proceed until the blocking condition is cleared.
Implementation note: The IIO does not do any read passing read performance
optimizations.
5.2.2.1 Inbound Writes Can Pass Outbound Completions
PCI Express allows inbound write requests to pass outbound read and outbound non-
posted write completions. For peer-to-peer traffic, this optimization allows writes to
memory to make progress while a PCI Express device is making long read requests to a
peer device on the same interface.
5.2.2.2 PCI Express Relaxed Ordering
The relaxed ordering attribute (RO) is a bit in the header of every PCI Express packet
and relaxes the ordering rules such that:
• Posted requests with RO set can pass other posted requests.
• Non-posted completions with RO set can pass posted requests.
The IIO relaxes write ordering for non-coherent, DRAM write transactions with this
attribute set. The IIO does not relax the ordering between read completions and
outbound posted transactions.
With the exception of peer-to-peer requests, the IIO clears the relaxed ordering for
outbound transactions received from the Intel
®
QPI Ordering Domain. For local and
remote peer-to-peer transactions, the attribute is preserved for both requests and
completions.