Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 313
IIO Ordering Model
5.2 Inbound Ordering Rules
Inbound transactions originate from PCI Express, Intel
®
QuickData Technology DMA, or
DMI and target main memory. In general, the IIO forwards inbound transactions in
FIFO order, with specific exceptions. For example, PCI Express requires that read
completions are allowed to pass stalled read requests. This forces read completions to
bypass any reads that might be back-pressured on Intel
®
QPI. Sequential, non-posted
requests are not required to be completed in the order in which they were requested.
1
Inbound writes are posted beyond the PCI Express ordering domain. Posting of writes
relies on the fact that the system maintains a certain ordering relationship. Since the
IIO cannot post inbound writes beyond the PCI Express ordering domain, the IIO must
wait for snoop responses before issuing subsequent, order-dependent transactions.
The IIO relaxes ordering between different PCI Express ports, aside from the peer-to-
peer restrictions below.
5.2.1 Inbound Ordering Requirements
In general, there are no ordering requirements between transactions received on
different PCI Express interfaces. The rules below apply to inbound transactions received
on the same interface.
RULE 1: Outbound non-posted read and non-posted write completions must be
allowed to progress past stalled inbound non-posted requests.
RULE 2: Inbound posted write requests and messages must be allowed to progress
past stalled inbound non-posted requests.
RULE 3: Inbound posted write requests, inbound messages, inbound read requests,
outbound non-posted read and outbound non-posted write completions
cannot pass enqueued inbound posted write requests.
The producer-consumer model prevents read requests, write requests, and non-posted
read or non-posted write completions from passing write requests. See the PCI Local
Bus Specification, Revision 2.3 for details on the producer-consumer ordering model.
RULE 4: Outbound non-posted read or outbound non-posted write completions must
push ahead all prior inbound posted transactions from that PCI Express port.
RULE 5: Inbound, coherent, posted writes will issue requests for ownership (RFO)
without waiting for prior ownership requests to complete. Local-local address
conflict checking still applies.
RULE 6: Since requests for ownership do not establish ordering, these requests can
be pipelined. Write ordering is established when the line transitions to the
“Modified” state.Inbound messages follow the same ordering rules as
inbound posted writes (FENCE messages have their own rules).
Inbound Read Completion
The completion for an inbound read. For example, the read data which
results in a PCI Express device read to main memory. While the data flows
outbound, the completion is still for an inbound read.
Inbound Write
A write issued toward an Intel
®
QPI component. This can be a write issued
by a PCI Express device. An obvious example is a PCI Express device writing
main memory. In the Intel
®
QPI domain, this write is often fragmented into
a request-for-ownership followed by an eventual writeback to memory.
Inbound Write Completion
Does not exist. All inbound writes are considered posted (in the PCI Express
context) and therefore, this term is never used in this chapter.
Table 99. Ordering Term Definitions (Sheet 2 of 2)
Term Definition
1. The DMI interface has exceptions to this rule as specified in Section 5.2.1.