Datasheet
IIO Ordering Model
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
312 Order Number: 323103-001
5.0 IIO Ordering Model
5.1 Introduction
The IIO spans two different ordering domains: one that adheres to producer-consumer
ordering (PCI Express*) and one that is unordered (Intel
®
QPI). One of the primary
functions of the IIO is to ensure that the producer-consumer ordering model is
maintained in the unordered, Intel
®
QPI domain.
This section describes the rules that are required to ensure that both PCI Express and
Intel
®
QPI ordering is preserved. Throughout this chapter, the following terms are
used:
Table 99. Ordering Term Definitions (Sheet 1 of 2)
Term Definition
Intel
®
QPI Ordering Domain
Intel
®
QPI has a relaxed ordering model allowing reads, writes and
completions to flow independent of each other. Intel
®
QPI implements this
through the use of multiple, independent virtual channels. With the
exception of the home channel, which maintains ordering to ensure
coherency, the Intel
®
QPI ordering domain is in general considered
unordered.
PCI Express Ordering Domain
PCI Express and all other prior PCI generations have specific ordering rules
to enable low cost components to support the producer-consumer model.
For example, no transaction can pass a write flowing in the same direction.
In addition, PCI implements ordering relaxations to avoid deadlocks (e.g.
completions must pass non-posted requests). The set of these rules are
described in PCI Express Base Specification, Revision 2.0.
Posted
A posted request is a request which can be considered ordered (per PCI
rules) upon the issue of the request and therefore completions are
unnecessary. The only posted transaction is PCI memory writes. Intel
®
QPI
does not implement posted semantics and so to adhere to the posted
semantics of PCI, the rules below are prescribed.
Non-posted
A non-posted request is a request which cannot be considered ordered (per
PCI rules) until after the completion is received. Non-posted transactions
include all reads and some writes (I/O and configuration writes). Since
Intel
®
QPI is largely unordered, all requests are considered to be non-
posted until the target responds. Through this chapter, the term non-posted
applies only to PCI requests.
Outbound Read
A read issued toward a PCI Express device. This can be a read issued by a
processor, an SMBus master, or a peer PCIe device.
Outbound Read Completion
The completion for an outbound read. For example, the read data which
results in a CPU read of a PCI Express device. While the data flows inbound,
the completion is still for an outbound read.
Outbound Write
A write issued toward a PCI Express device. This can be a write issued by a
processor, an SMBus master, or a peer PCIe device.
Outbound Write Completion
The completion for an outbound write. For example, the completion from a
PCI Express device which results from a CPU-initiated I/O or configuration
write. While the completion flows inbound, the completion is still for an
outbound write.
Inbound Read
A read issued toward an Intel
®
QPI component. This can be a read issued
by a PCI Express device. An obvious example is a PCI Express device
reading main memory.