Datasheet

Technologies
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
310 Order Number: 323103-001
• Effective move BW of 2.5 GB/s (2.5 GB/s effective read + 2.5 GB/s effective write),
calculated assuming descriptor batch size of 2 and a data payload size of 1460 B.
• Raw BW of 5 GB/s read + 5 GB/s write.
• Eight independent DMA Channels where each channel is compliant with Intel
®
QuickData Technology versions 3 and 2, but not compatible with version 1.
• Data transfer between two system memory locations, or from system memory to
MMIO.
• CRC-32 Generation and Check.
• Flow through CRC.
• Marker Skipping.
•Page Zeroing.
• 40 bits of addressing, though the Intel
®
QuickData Technology DMA BAR still
supports the PCI compliant 64bit BAR. Software is expected to program the BAR to
less than 2^40, otherwise an error is generated. Similarly for DMA accesses
generated by the DMA controller.
• Maximum transfer length of 1 MB per DMA descriptor block.
• Both coherent and non-coherent memory transfer on a per descriptor basis with
independent control of coherency for source and destination.
• Support for relaxed ordering for transactions to main memory.
• Support for deep pipelining in each channel independently; i.e. while a DMA
channel is servicing the descriptor/data-payload for one move operation, it
pipelines the descriptor and data payload for the next move (if there is one)
• Programmable mechanisms for signaling the completion of a descriptor by
generating an MSI-X interrupt or legacy level-sensitive interrupt.
• Programmable mechanism for signaling the completion of a descriptor by
performing an outbound write of the completion status.
• Deterministic error handling during transfer by aborting the transfer and also
permitting the controlling process to abort the transfer via command register bits.
• MSI-X with 1 vector per function.
• Interrupt coalescing.
• Support for FLR independently for each DMA engine. Allows for individual Intel
®
QuickData Technology DMA channels to be reset and reassigned across VMs.
•Intel
®
QuickData Technology DMA transactions are translated via Intel
®
VT-d.
4.2.1.6.2 Unsupported Features
The following features are not supported by the DMA controller:
• DMA data transfer from I/O subsystem to local system memory, and I/O to I/O
subsystems are not supported.
• Backward compatibility to Intel
®
QuickData Technology Version 1 specifications.
• Hardware model for controlling Intel
®
QuickData Technology DMA via NIC
hardware.
• No support for CB_Query message to unlock DMA.