Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 31
Features Summary
1.5 Power Management Support
1.5.1 Processor Core
• Full support of ACPI C-states as implemented by the following processor core &
package C-states:
— Core: C0, C1E, C3, C6
— Package: C0, C3, C6
• Enhanced Intel SpeedStep
®
Technology
1.5.2 System
• S0, S1, S3, S4, S5
1.5.3 Memory Controller
• Conditional self-refresh (Intel
®
Rapid Memory Power Management (Intel
®
RMPM)
• Dynamic power-down
• Asynchronous DRAM Refresh
1.5.4 PCI Express
• L0, L0s, L1, L3
1.5.5 DMI
• L0, L0s, L1, L3
1.5.6 Intel
®
QuickPath Interconnect
• L0, L0s, and L1
1.6 Thermal Management Support
PECI (Platform Environment Control Interface) is a serial processor interface used
primarily for thermal power and error management. The PECI data may be read by the
PCH or by a BMC or other external logic.
The Intel
®
Xeon
®
processor C5500/C3500 series contains six digital thermal sensors –
one for each core, one for uncore, and one for the IIO portion of the die. The time
average temperature, of the thermal sensor indicating the highest temperature, is
reported via the PECI bus. This reflects the maximum die temperature. These five
digital thermal sensors are used to initiate Adaptive Intel
®
Thermal Monitor.
1.7 Package
The Intel
®
Xeon
®
processor C5500/C3500 series socket type is noted as Socket B. The
package is a 42.5X45.0mm Flip Chip Land Grid Array (LGA/FCLGA1366), with a 40-mil
land pitch.