Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 309
Technologies
4.2.1 Intel
®
QuickData Technology
Intel
®
QuickData Technology makes Intel
®
chipsets excel with Intel network
controllers. The Intel
®
Xeon
®
processor C5500/C3500 series uses the third generation
of the Intel
®
QuickData Technology.
The Intel
®
Xeon
®
processor C5500/C3500 series supports Intel
®
QuickData
Technology. A NIC that is Intel
®
QuickData Technology capable can be plugged into any
of the processor PCIe* ports, or be plugged into a PCIe ports below the PCH, and use
the Intel
®
QuickData Technology capabilities.
4.2.1.1 Port/Stream Priority
The Intel
®
Xeon
®
processor C5500/C3500 series does not support port or stream
priority.
4.2.1.2 Write Combining
The Intel
®
Xeon
®
processor C5500/C3500 series does not support the Intel
®
QuickData Technology write combining feature.
4.2.1.3 Marker Skipping
The DMA engine can copy a block of data from a source buffer to a destination buffer,
and can be programmed to skip bytes (marker) in the source buffer, eliminating their
position in the destination buffer (i.e. destination data is packed).
4.2.1.4 Buffer Hint
A bit in the Descriptor Control Register, which when set, provides guidance to the HW
that some or all of the data processed by the descriptor may be referenced again in a
subsequent descriptor. Software sets this bit if the source data will most likely be
specified in another descriptor of this bundle. “Bundle” indicates descriptors that are in
a group. When the Bundle bit is set in the Descriptor Control Register, the descriptor is
associated with the next descriptor, creating a descriptor bundle. Thus each descriptor
in the bundle has “Bundle=1” except for the last one, which has Bundle=0.
4.2.1.5 DCA
The Intel
®
Xeon
®
processor C5500/C3500 series supports DCA from both the DMA
engine (on both payload and completion writes) and the PCIe ports.
4.2.1.6 DMA
The Intel
®
Xeon
®
processor C5500/C3500 series incorporates a high performance DMA
engine optimized primarily for moving data between memory. The DMA also supports
moving data between memory and MMIO (push data packet size to PCIe is limited to a
maximum size of 64B).
There are eight software-visible Intel
®
QuickData Technology DMA engines (i.e. eight
PCI functions) and each DMA engine has one channel. These channels are concurrent
and conform to the Intel
®
QuickData Technology specification. Each DMA engine can be
independently assigned to a VM in a virtualized system.
4.2.1.6.1 Supported Features
The following features are supported by the DMA engine: