Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 305
PCI Express Non-Transparent Bridge
3.21.3.3 SMSIXVECCNTL[0-3]: Secondary MSI-X Vector Control Register 0 - 3
3.21.3.4 SMSIXPBA: Secondary MSI-X Pending Bit Array Register
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Register:SMSIXVECCNTLn
Bar:PB01BASE, SB01BASE
Offset:0000400Ch, 0000401Ch, 0000402Ch, 0000403Ch
Bit Attr Default Description
31:01 RO 00000000h Reserved
00 RW 1b
MSI-X Mask:
When this bit is set, the NTB is prohibited from sending a message using this
MSI-X Table entry. However, any other MSI-X Table entries programmed with
the same vector will still be capable of sending an equivalent message unless
they are also masked.
Register:S
MSIXPBA
Bar:PB01BASE, SB01BASE
Offset:00005000h
Bit Attr Default Description
31:04 RO 0000h Reserved
03 RO 0b MSI-X Table Entry 03 (NTB) has a Pending Message.
02 RO 0b MSI-X Table Entry 02 (NTB) has a Pending Message.
01 RO 0b MSI-X Table Entry 01 (NTB) has a Pending Message.
00 RO 0b MSI-X Table Entry 00 (NTB) has a Pending Message.