Datasheet

PCI Express Non-Transparent Bridge
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
304 Order Number: 323103-001
3.21.3.1 SMSIXTBL[0-3]: Secondary MSI-X Table Address Register 0 - 3
.
3.21.3.2 SMSIXDATA[0-3]: Secondary MSI-X Message Data Register 0 - 3
SDOORBELL bits to MSI-X mapping can be reprogrammed through Section 3.21.1.22,
“RSDBMSIXV70: Route Secondary Doorbell MSI-X Vector 7 to 0” and
Section 3.21.1.23, “RSDBMSIXV158: Route Secondary Doorbell MSI-X Vector 15 to 8”
Register:SMSIXTBLn
Bar:PB01BASE, SB01BASE
Offset:00004000h, 00004010h, 00004020h, 00004030h
Bit Attr Default Description
63:32 RW 00000000h
MSI-X Upper Address
Upper address bits used when generating an MSI-X.
31:02 RW 00000000h
MSI-X Address
System-specified message lower address. For MSI-X messages, the contents
of this field from an MSI-X Table entry specifies the lower portion of the
DWORD-aligned address (AD[31:02]) for the memory write transaction.
01:00 RO 00b
MSG_ADD10
For proper DWORD alignment, these bits need to be 0’s.
Register:SMSIXDATAn
Bar:PB01BASE, SB01BASE
Offset:00004008h, 00004018h, 00004028h, 00004038h
Bit Attr Default Description
31:00 RW 0000h
Message Data
System-specified message data.
Table 98. MSI-X Vector Handling and Processing by IIO on Secondary Side
Number of Messages Enabled by Software Events IV[7:0]
1All
xxxxxxxx
1
1. The term “xxxxxx” in the Interrupt vector denotes that software initializes them and IIO will not modify any of the “x” bits
4
PD[04:00]
xxxxxxxx
PD[09:05] xxxxxxxx
PD[14:10] xxxxxxxx
PD[15] xxxxxxxx