Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 303
PCI Express Non-Transparent Bridge
3.21.3 MSI-X MMIO registers (NTB Secondary Side)
Secondary side MSI-X MMIO registers reached via PB01BASE (debug) and SB01BASE.
These registers are valid when in NTB/RP configuration.
Table 97. NTB MMIO Map
SMSIXTLB0
4000h
SMSIXPBA
5000h
4004h
5004h
SMSIXDATA0
4008h 5008h
SMSIXVECCNTL0
400Ch 500Ch
SMSIXTLB1
4010h 5010h
4014h
5014h
SMSIXDATA1
4018h 5018h
SMSIXVECCNTL1
401Ch 501Ch
SMSIXTLB2
4020h 5020h
4024h
5024h
SMSIXDATA2
4028h 5028h
SMSIXVECCNTL2
402Ch 502Ch
SMSIXTLB3
4030h 5030h
4034h
5034h
SMSIXDATA3
4038h 5038h
SMSIXVECCNTL3
403Ch 503Ch
4040h 5040h
4044h 5044h
4048h 5048h
404Ch 504Ch