Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 301
PCI Express Non-Transparent Bridge
3.21.2.1 PMSIXTBL[0-3]: Primary MSI-X Table Address Register 0 - 3
.
3.21.2.2 PMSIXDATA[0-3]: Primary MSI-X Message Data Register 0 - 3
3.21.2.3 PMSIXVECCNTL[0-3]: Primary MSI-X Vector Control Register 0 - 3
Register:PMSIXTBLn
Bar:PB01BASE, SB01BASE
Offset:00002000h, 00002010h, 00002020h, 00002030h
Bit Attr Default Description
63:32 RW 00000000h
MSI-X Upper Address
Upper address bits used when generating an MSI-X.
31:02 RW 00000000h
MSI-X Address
System-specified message lower address. For MSI-X messages, the contents
of this field from an MSI-X Table entry specifies the lower portion of the
DWORD-aligned address (AD[31:02]) for the memory write transaction.
01:00 RO 00b
MSG_ADD10
For proper DWORD alignment, these bits need to be 0’s.
Register:P
MSIXDATAn
Bar:PB01BASE, SB01BASE
Offset:00002008h, 00002018h, 00002028h, 00002038h
Bit Attr Default Description
31:00 RW 0000h
Message Data
System-specified message data.
Table 96. MSI-X Vector Handling and Processing by IIO on Primary Side
Number of Messages enabled by Software Events IV[7:0]
1All
xxxxxxxx
1
1. The term “xxxxxx” in the Interrupt vector denotes that software initializes them and IIO will not modify any of the “x” bits
4
PD[04:00]
xxxxxxxx
PD[09:05] xxxxxxxx
PD[14:10] xxxxxxxx
HP, BW-change, AER,
PD[15]
xxxxxxxx
Register:PMSIXVECCNTLn
Bar:PB01BASE, SB01BASE
Offset:0000200Ch, 0000201Ch, 0000202Ch, 0000203Ch
Bit Attr Default Description
31:01 RO 00000000h Reserved
00 RW 1b
MSI-X Mask
When this bit is set, the NTB is prohibited from sending a message using this
MSI-X Table entry. However, any other MSI-X Table entries programmed with
the same vector will still be capable of sending an equivalent message unless
they are also masked.