Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 3
Contents
1.0 Features Summary ..................................................................................................24
1.1 Introduction .....................................................................................................24
1.2 Processor Feature Details ...................................................................................27
1.2.1 Supported Technologies ..........................................................................27
1.3 SKUs...............................................................................................................27
1.4 Interfaces ........................................................................................................28
1.4.1 Intel
®
QuickPath Interconnect (Intel
®
QPI) ...............................................28
1.4.2 System Memory Support.........................................................................28
1.4.3 PCI Express...........................................................................................29
1.4.4 Direct Media Interface (DMI)....................................................................30
1.4.5 Platform Environment Control Interface (PECI)...........................................30
1.4.6 SMBus..................................................................................................30
1.5 Power Management Support ...............................................................................31
1.5.1 Processor Core.......................................................................................31
1.5.2 System.................................................................................................31
1.5.3 Memory Controller..................................................................................31
1.5.4 PCI Express...........................................................................................31
1.5.5 DMI......................................................................................................31
1.5.6 Intel
®
QuickPath Interconnect .................................................................31
1.6 Thermal Management Support ............................................................................31
1.7 Package...........................................................................................................31
1.8 Terminology ..................................................................................................... 32
1.9 Related Documents ...........................................................................................33
2.0 Interfaces................................................................................................................35
2.1 System Memory Interface ..................................................................................35
2.1.1 System Memory Technology Supported.....................................................35
2.1.2 System Memory DIMM Configuration Support.............................................36
2.1.3 System Memory Timing Support...............................................................37
2.1.3.1 System Memory Operating Modes .............................................38
2.1.3.2 Single-Channel Mode...............................................................39
2.1.3.3 Independent Channel Mode......................................................39
2.1.3.4 Spare Channel Mode................................................................40
2.1.3.5 Mirrored Channel Mode............................................................41
2.1.3.6 Lockstep Mode........................................................................42
2.1.3.7 Dual/Triple - Channel Modes.....................................................43
2.1.4 DIMM Population Requirements................................................................45
2.1.4.1 General Population Requirements..............................................45
2.1.4.2 Populating DIMMs Within a Channel...........................................45
2.1.4.3 Channel Population Requirements for Memory RAS Modes ............ 48
2.1.5 Technology Enhancements of Intel
®
Fast Memory Access (Intel
®
FMA)..........48
2.1.5.1 Just-in-Time Command Scheduling............................................48
2.1.5.2 Command Overlap ..................................................................49
2.1.5.3 Out-of-Order Scheduling..........................................................49
2.1.6 DDR3 On-Die Termination .......................................................................49
2.1.7 Memory Error Signaling...........................................................................49
2.1.7.1 Enabling SMI/NMI for Memory Corrected Errors...........................50
2.1.7.2 Per DIMM Error Counters .........................................................50
2.1.7.3 Identifying the Cause of An Interrupt.........................................51
2.1.8 Single Device Data Correction (SDDC) Support...........................................51
2.1.9 Patrol Scrub ..........................................................................................51
2.1.10 Memory Address Decode.........................................................................52
2.1.10.1 First Level Decode...................................................................52