Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 299
PCI Express Non-Transparent Bridge
3.21.1.27 B2BBAR0XLAT: Back-to-Back BAR 0/1 Translate
This register is valid when in NTB/NTB configuration. This register is used to set the
base address where the back-to-back doorbell and scratchpad packets will be sent. This
register must match the base address loaded into the BAR 0/1 pair on the opposite
NTB, whose Secondary side in linked to the Secondary side of this NTB.
Note: There is no hardware enforced limit for this register, care must be taken when setting
this register to stay within the addressable range of the attached system.
Register:B2BBAR0XLAT
Bar:PB01BASE, SB01BASE
Offset:144h
Bit Attr Default Description
63:15
Bar: Attr
PB01BASE:
RW
else: RO
0000h
B2B translate
Base address of Secondary BAR 0/1 on the opposite NTB
14:00 RO 00h
Reserved
Limit register has a granularity of 32 KB (2
15
)