Datasheet

PCI Express Non-Transparent Bridge

Intel

Xeon

Processor C5500/C3500 Series

Datasheet, Volume 1 February 2010

296 Order Number: 323103-001

3.21.1.23 RSDBMSIXV158: Route Secondary Doorbell MSI-X Vector 15 to 8

This register is used to allow flexibility in the SDOORBELL Section 3.21.1.17,

“SDOORBELL: Secondary Doorbell” bits 15 to 8 assignments to one of 4 MSI-X vectors.

Bar:PB01BASE

Offset:D4h

Bit Attr Default Description

31:30 RO 0h Reserved

29:28 RW 3h MSI-X Vector assignment for SDOORBELL bit 15

27:26 RO 0h Reserved

25:24 RW 2h

MSI-X Vector assignment for SDOORBELL bit 14

23:22 RO 0h Reserved

21:20 RW 2h MSI-X Vector assignment for SDOORBELL bit 13

19:18 RO 0h Reserved

17:16 RW 2h MSI-X Vector assignment for SDOORBELL bit 12

15:14 RO 0h Reserved

13:12 RW 2h MSI-X Vector assignment for SDOORBELL bit 11

11:10 RO 0h Reserved

09:08 RW 2h MSI-X Vector assignment for SDOORBELL bit 10

07:06 RO 0h Reserved

05:04 RW 1h MSI-X Vector assignment for SDOORBELL bit 9

03:02 RO 0h Reserved

01:00 RW 1h

MSI-X Vector assignment for SDOORBELL bit 8

11 = MSI-X vector allocation 3

10 = MSI-X vector allocation 2

01 = MSI-X vector allocation 1

00 = MSI-X vector allocation 0